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1. 发明授权

US07340552B2 Bus control system 失效
标题翻译：总线控制系统
公开(公告)号：US07340552B2
公开(公告)日：2008-03-04
申请号：US11642511
申请日：2006-12-21
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
摘要翻译：在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

2. 发明申请

US20050111171A1 Information processing unit and information processing related units 有权
标题翻译：信息处理单元和信息处理相关单位
公开(公告)号：US20050111171A1
公开(公告)日：2005-05-26
申请号：US11011189
申请日：2004-12-15
申请人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
发明人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
IPC分类号： G06F15/02 , E05B73/00 , G06F1/16 , G06F1/26 , G06F3/00
CPC分类号： G06F1/1616 , E05B73/0005 , E05B73/0082 , G06F1/1632 , G06F1/1635 , G06F1/1656 , G06F1/266
摘要： A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD·D or a CD ROM·D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator can omit the labor of disconnecting many cables connected to the portreplicator.
摘要翻译：即使携带具有与主体一起加载的外部存储器的文件基站，也省略了断开许多电缆的工作。信息处理单元包括：具有CPU，键盘和显示单元的主体; 具有外部存储器的文件基站，例如FD.D或CD ROM.D，加载; 和一个具有许多连接器的portreplicator。主机从复印机中单独拆卸可以省去断开连接到复印机的许多电缆的工作。

3. 发明授权

US06898078B2 Information processing unit and information processing related units 有权
标题翻译：信息处理单元和信息处理相关单位
公开(公告)号：US06898078B2
公开(公告)日：2005-05-24
申请号：US10178745
申请日：2002-06-25
申请人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
发明人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
IPC分类号： G06F15/02 , E05B73/00 , G06F1/16 , G06F1/26 , G06F3/00
CPC分类号： G06F1/1616 , E05B73/0005 , E05B73/0082 , G06F1/1632 , G06F1/1635 , G06F1/1656 , G06F1/266
摘要： A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD•D or a CD-ROM•D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.
摘要翻译：即使携带具有与主体一起加载的外部存储器的文件基站，也省略了断开许多电缆的工作。信息处理单元包括：具有CPU，键盘和显示单元的主体; 具有外部存储器的文件基站，例如FD.D或CD-ROM.D，加载; 和一个具有许多连接器的portreplicator。主机单独从复印机拆卸或拆除主体和文件基站可以省去断开连接到复印机的许多电缆的工作。

4. 发明授权

US6047345A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
公开(公告)号：US6047345A
公开(公告)日：2000-04-04
申请号：US78713
申请日：1998-05-14
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

5. 发明授权

US5881255A Bus control system incorporating the coupling of two split-transaction busses of different hierarchy 失效
公开(公告)号：US5881255A
公开(公告)日：1999-03-09
申请号：US847974
申请日：1997-04-21
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/36 , G06F3/00 , G06F5/00 , G06F13/00 , G06F13/368 , G06F13/40 , G06F12/00
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

6. 发明授权

US5671371A Bus control system 失效
标题翻译：总线控制系统
公开(公告)号：US5671371A
公开(公告)日：1997-09-23
申请号：US544727
申请日：1995-10-18
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/36 , G06F3/00 , G06F5/00 , G06F13/00 , G06F13/368 , G06F13/40 , G06I13/00
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
摘要翻译：在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

7. 发明授权

US4910704A Terminal controller with buffer memories storing edited screen data and control method therefor 失效
标题翻译：具有存储编辑画面数据的缓冲存储器的终端控制器及其控制方法
公开(公告)号：US4910704A
公开(公告)日：1990-03-20
申请号：US476853
申请日：1983-03-18
申请人： Hideaki Gemma
发明人： Hideaki Gemma
IPC分类号： G06F3/153 , G06F3/048 , G06F3/14 , G06T1/00 , G06T11/00 , G09G5/36 , G09G5/39 , G09G5/395
CPC分类号： G09G5/395 , G06F3/1431 , G09G5/363
摘要： The invention relates to a terminal controller for editing formatted screen data sent from a processing unit to produce edited screen data and for transferring the edited screen data to a terminal device. The edited screen data which can be repeatedly used is stored in a buffer memory which is separately provided in the terminal controller. In response to a command from the processing unit, this data is extracted from the buffer memory so that the screen data is transferred to the terminal device without being re-edited for each transfer. The data stored in the buffer memory is subjected, if desired, to a synthesizing processing before it is sent to the terminal device.
摘要翻译：本发明涉及一种终端控制器，用于编辑从处理单元发送的格式化屏幕数据，以产生编辑的屏幕数据，并将编辑的屏幕数据传送到终端设备。可以重复使用的编辑画面数据存储在分离设置在终端控制器中的缓冲存储器中。响应于来自处理单元的命令，从缓冲存储器中提取该数据，使得屏幕数据被传送到终端设备而不被重新编辑用于每次传送。如果需要，存储在缓冲存储器中的数据在被发送到终端设备之前被进行合成处理。

8. 发明申请

US20070106832A1 Bus control system 失效
公开(公告)号：US20070106832A1
公开(公告)日：2007-05-10
申请号：US11642511
申请日：2006-12-21
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

9. 发明授权

US06606243B2 Information processing unit and information processing related units 有权
公开(公告)号：US06606243B2
公开(公告)日：2003-08-12
申请号：US09788529
申请日：2001-02-21
申请人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
发明人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
IPC分类号： G06F116
CPC分类号： G06F1/1616 , E05B73/0005 , E05B73/0082 , G06F1/1632 , G06F1/1635 , G06F1/1656 , G06F1/266
摘要： A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD·D or a CD-ROM·D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.

10. 发明授权

US5657458A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
标题翻译：用于控制总线进行传送周期而不插入确认周期的方法
公开(公告)号：US5657458A
公开(公告)日：1997-08-12
申请号：US480397
申请日：1995-06-07
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.
摘要翻译：一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的总线主控性，并且同时断言最后一个周期信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。读取权限后，主人释放总线主控权。只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

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