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1. 发明授权

US5787008A Simulation corrected sensitivity 失效
标题翻译：模拟校正灵敏度
公开(公告)号：US5787008A
公开(公告)日：1998-07-28
申请号：US629488
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

2. 发明授权

US5790415A Complementary network reduction for load modeling 失效
标题翻译：用于负载建模的互补网络简化
公开(公告)号：US5790415A
公开(公告)日：1998-08-04
申请号：US630189
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

3. 发明授权

US5751593A Accurate delay prediction based on multi-model analysis 失效
标题翻译：基于多模型分析的精确延迟预测
公开(公告)号：US5751593A
公开(公告)日：1998-05-12
申请号：US629487
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于调整尺寸增加的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

4. 发明授权

US07149674B1 Methods for analyzing integrated circuits and apparatus therefor 失效
标题翻译：用于分析集成电路的方法及其装置
公开(公告)号：US07149674B1
公开(公告)日：2006-12-12
申请号：US09580854
申请日：2000-05-30
申请人： Supamas Sirichotiyakul , David T. Blaauw , Timothy J. Edwards , Chanhee Oh , Rajendran V. Panda , Judah L. Adelman , David Moshe , Abhijit Dharchoudhury
发明人： Supamas Sirichotiyakul , David T. Blaauw , Timothy J. Edwards , Chanhee Oh , Rajendran V. Panda , Judah L. Adelman , David Moshe , Abhijit Dharchoudhury
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.
摘要翻译：公开了一种提高双电位集成电路性能的方法，其中针对具有第一阈值电压电平的集成电路的每个晶体管计算第一值。第一个值至少部分地基于如同对应的晶体管具有第二阈值电压电平那样计算的延迟和泄漏。然后基于第一值选择一个晶体管。然后将所选择的晶体管的阈值电压设置为第二阈值电压电平。电路内的至少一个晶体管的面积被修改，然后将电路的尺寸设定到预定区域。如果电路性能不能满足规定的约束，则可以重复该过程。在一个实施例中，性能确定包括计算电路被分配到其中的一组DC连接组件的漏电流，确定每个组件的主要逻辑状态，估计这些主要逻辑状态中的每一个的泄漏，以及求和基于状态概率的这些主成分的加权平均值。

5. 发明授权

US5689432A Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method 失效
标题翻译：集成电路设计和制造方法以及根据该方法设计集成电路的装置
公开(公告)号：US5689432A
公开(公告)日：1997-11-18
申请号：US373695
申请日：1995-01-17
申请人： David T. Blaauw , Robert L. Maziasz , Joseph W. Norton , Larry G. Jones , Mohankumar Guruswamy
发明人： David T. Blaauw , Robert L. Maziasz , Joseph W. Norton , Larry G. Jones , Mohankumar Guruswamy
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： H01L27/0207 , G06F17/505 , G06F17/5068
摘要： A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plurality of interconnected logic gate functions to duplicate the operation of the BCM. The gates in the data file are then assigned a specific Vdd and ground rail size, a specific drive strength for speed considerations, and a cell pitch or height to optimize physical layout, in any order. The result in a physical design file which may be used to form masks and integrated circuits having optimized speed and optimized circuit area in a short design cycle.
摘要翻译：集成电路的设计方法涉及四步法。首先，读取行为电路模型（BCM），其包含识别集成电路（IC）的逻辑运算的分配语句。将BCM转换为描述多个互连的逻辑门功能以复制BCM的操作的数据文件。然后，以任何顺序，将数据文件中的门分配特定的Vdd和地面轨道尺寸，速度考虑的特定驱动强度以及单元间距或高度来优化物理布局。物理设计文件的结果可以用于形成具有优化速度的掩模和集成电路，并在短的设计周期内优化电路面积。

6. 发明授权

US5619418A Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized 失效
标题翻译：用于集成电路的逻辑门尺寸优化处理，从而在优化电路面积的同时提高电路速度
公开(公告)号：US5619418A
公开(公告)日：1997-04-08
申请号：US390210
申请日：1995-02-16
申请人： David T. Blaauw , Joseph W. Norton , Larry G. Jones , Susanta Misra , R. Iris Bahar
发明人： David T. Blaauw , Joseph W. Norton , Larry G. Jones , Susanta Misra , R. Iris Bahar
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity=.DELTA.speed/.DELTA.area) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area. The above process continues iteratively until no out-of-specification circuit paths are found.
摘要翻译：集成电路在设计时必须遵守时序约束，同时尽量减少电路面积。为了在达到近似最佳电路表面积的同时遵循定时规范，使用迭代过程，其通过从存储器存储逻辑门库访问逻辑门来选择性地增加逻辑门大小。电路表示与电路路径的时序约束一起读取。处理电路中的每个电路路径以找到其实际的电路路径延迟。在电路中选择最不符合规范的电路路径（在速度方面），并且在最规范的电路路径中对每个逻辑门执行灵敏度计算。具有最大灵敏度（灵敏度= DELTA速度/ DELTA面积）的电路路径中的逻辑门的大小通过访问库中较大的门而增加，以便以面积为代价来提高速度。上述过程继续进行，直到找不到超出规范的电路路径。

7. 发明授权

US07093223B2 Noise analysis for an integrated circuit model 有权
标题翻译：集成电路模型的噪声分析
公开(公告)号：US07093223B2
公开(公告)日：2006-08-15
申请号：US10304423
申请日：2002-11-26
申请人： Murat R. Becer , Ilan Algor , Rajendran V. Panda , David T. Blaauw
发明人： Murat R. Becer , Ilan Algor , Rajendran V. Panda , David T. Blaauw
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.
摘要翻译：一种减少串扰的设计和布线电路的方法。在全局路由（12）之后但在详细路由（28）之前执行早期噪声分析（22），以便在执行详细路由（28）之前修复问题（24）。在一个实施例中，早期噪声分析（22）之前是概率抽取（16）。在一个实施例中，概率提取（16）包括确定在预定的一组配置（54）中的每个配置的发生概率。然后进行概率电容提取（56）。使用提取的电容（60）构建概率分布耦合RC网络。在一个实施例中，概率提取（16）包括使用概率分布耦合RC网络估计攻击者强度（20）。

8. 发明授权

US06819538B2 Method and apparatus for controlling current demand in an integrated circuit 有权
标题翻译：用于控制集成电路中的电流需求的方法和装置
公开(公告)号：US06819538B2
公开(公告)日：2004-11-16
申请号：US09858126
申请日：2001-05-15
申请人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
发明人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
IPC分类号： H02H300
CPC分类号： G06F1/305
摘要： The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.
摘要翻译：本发明一般涉及用于控制集成电路中的电流需求的方法和装置。一个实施例涉及一种方法，其包括检测是否存在电源电压过冲或下冲，并且如果检测到的话，控制消耗电力消耗的电流以确保电源电压保持在可接受的水平内。其他实施例涉及具有电容去耦结构，功耗电路和功耗控制电路的集成电路，用于控制由功耗电路的至少一部分消耗的电流。因此，本发明的实施例涉及监视和控制功耗电路（例如集成电路）的功耗（即电流需求），以便防止毁坏性的电源电压欠冲，过冲和振荡。

9. 发明授权

US06799153B1 Cross coupling delay characterization for integrated circuits 失效
标题翻译：集成电路的交叉耦合延迟特性
公开(公告)号：US06799153B1
公开(公告)日：2004-09-28
申请号：US09553271
申请日：2000-04-20
申请人： Supamas Sirichotiyakul , David T. Blaauw , Chanhee Oh , Vladimir P. Zolotov , Rafi Levy
发明人： Supamas Sirichotiyakul , David T. Blaauw , Chanhee Oh , Vladimir P. Zolotov , Rafi Levy
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor. Accurate delay characterization provides for design engineers an accurate description of the worst case and best case scenarios of the integrated circuit or microprocessor that is needed for various applications such as the integration of the integrated circuit and microprocessor into a larger system.
摘要翻译：对集成电路和其他微处理器应用执行交叉耦合延迟特性的解决方案。本发明在各种时间适当地对各种配置的集成电路建模，以适应与驱动器电路相关联的非线性以及集成电路内的网络之间的不期望的电容耦合，特别是那些位于彼此非常接近并且产生有害的司机过渡的影响从低到高，从高到低。本发明提供了一种计算上有效的解决方案来执行微处理器内各个转换操作的加速和减慢的延迟表征。精确的延迟表征为设计工程师提供了对于各种应用所需的集成电路或微处理器的最坏情况和最佳情况的精确描述，例如将集成电路和微处理器集成到更大的系统中。

10. 发明申请

US20120030268A1 Randomized value generation 有权
标题翻译：随机值生成
公开(公告)号：US20120030268A1
公开(公告)日：2012-02-02
申请号：US13067470
申请日：2011-06-02
申请人： Nurrachman Chih Yeh Liu , Scott M. Hanson , Nathaniel Pinckney , David T. Blaauw , Dennis M. Sylvester
发明人： Nurrachman Chih Yeh Liu , Scott M. Hanson , Nathaniel Pinckney , David T. Blaauw , Dennis M. Sylvester
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H03K3/84 , H04L9/001 , H04L9/0866
摘要： A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.
摘要翻译：提供了一种用于产生随机化值的数据处理装置。数据处理设备中的单元包括电介质氧化物层，并且应力电压电路被配置为在电池的电介质氧化物层上施加应力电压以引起氧化物击穿过程。氧化物击穿检测电路被配置为通过测量电介质氧化物层对应力电压的响应来确定氧化物击穿过程的当前范围，并且随机化值确定电路被配置为根据氧化物的当前范围确定随机化值分解过程

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