专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06819538B2 Method and apparatus for controlling current demand in an integrated circuit 有权
标题翻译：用于控制集成电路中的电流需求的方法和装置
公开(公告)号：US06819538B2
公开(公告)日：2004-11-16
申请号：US09858126
申请日：2001-05-15
申请人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
发明人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
IPC分类号： H02H300
CPC分类号： G06F1/305
摘要： The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.
摘要翻译：本发明一般涉及用于控制集成电路中的电流需求的方法和装置。一个实施例涉及一种方法，其包括检测是否存在电源电压过冲或下冲，并且如果检测到的话，控制消耗电力消耗的电流以确保电源电压保持在可接受的水平内。其他实施例涉及具有电容去耦结构，功耗电路和功耗控制电路的集成电路，用于控制由功耗电路的至少一部分消耗的电流。因此，本发明的实施例涉及监视和控制功耗电路（例如集成电路）的功耗（即电流需求），以便防止毁坏性的电源电压欠冲，过冲和振荡。

2. 发明授权

US07127384B2 Fast simulation of circuitry having SOI transistors 失效
标题翻译：具有SOI晶体管的电路的快速仿真
公开(公告)号：US07127384B2
公开(公告)日：2006-10-24
申请号：US10333432
申请日：2002-08-27
申请人： Vladimir P. Zolotov , Rajendran V. Panda , Sergey V. Gavrilov , Alexey L. Glebov , Yury B. Egorov , Dmitry Y. Nadexhin
发明人： Vladimir P. Zolotov , Rajendran V. Panda , Sergey V. Gavrilov , Alexey L. Glebov , Yury B. Egorov , Dmitry Y. Nadexhin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022
摘要： A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.
摘要翻译： SOI MOS电路的快速瞬态模拟器使用快速准确的SOI晶体管表模型。模拟器使用具有分区的电路的表示。通过数值求解描述其瞬态行为的微分方程，每个分区通过简单的时间步长分别进行模拟。以事件驱动的方式模拟整个电路的行为，其中每个事件对应于每个分区的积分时间步长。代替体电压，模拟器实现了一种变换，并将身体电荷作为一个独立的变量，以获得高精度和高速度的模拟。 SOI晶体管表模型的构建导致速度和精度的提高。该转换允许通过SOI晶体管背栅极电容近似恒定的事实减少表尺寸数量。

3. 发明授权

US07251797B2 Pessimism reduction in crosstalk noise aware static timing analysis 失效
标题翻译：串扰噪声感知静态时序分析的悲观主义减少
公开(公告)号：US07251797B2
公开(公告)日：2007-07-31
申请号：US10994858
申请日：2004-11-22
申请人： Murat R. Becer , Ilan Algor , Amir Grinshpon , Rafi Levy , Chanhee Oh , Rajendran V. Panda , Vladimir P. Zolotov
发明人： Murat R. Becer , Ilan Algor , Amir Grinshpon , Rafi Levy , Chanhee Oh , Rajendran V. Panda , Vladimir P. Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.
摘要翻译：用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何部分316对受害者时机的影响超出受害者定时窗口。有效的延迟时间用于调整受害者计时窗口。基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u 1）（613,625）。

4. 发明授权

US06799153B1 Cross coupling delay characterization for integrated circuits 失效
标题翻译：集成电路的交叉耦合延迟特性
公开(公告)号：US06799153B1
公开(公告)日：2004-09-28
申请号：US09553271
申请日：2000-04-20
申请人： Supamas Sirichotiyakul , David T. Blaauw , Chanhee Oh , Vladimir P. Zolotov , Rafi Levy
发明人： Supamas Sirichotiyakul , David T. Blaauw , Chanhee Oh , Vladimir P. Zolotov , Rafi Levy
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor. Accurate delay characterization provides for design engineers an accurate description of the worst case and best case scenarios of the integrated circuit or microprocessor that is needed for various applications such as the integration of the integrated circuit and microprocessor into a larger system.
摘要翻译：对集成电路和其他微处理器应用执行交叉耦合延迟特性的解决方案。本发明在各种时间适当地对各种配置的集成电路建模，以适应与驱动器电路相关联的非线性以及集成电路内的网络之间的不期望的电容耦合，特别是那些位于彼此非常接近并且产生有害的司机过渡的影响从低到高，从高到低。本发明提供了一种计算上有效的解决方案来执行微处理器内各个转换操作的加速和减慢的延迟表征。精确的延迟表征为设计工程师提供了对于各种应用所需的集成电路或微处理器的最坏情况和最佳情况的精确描述，例如将集成电路和微处理器集成到更大的系统中。

5. 发明授权

US08510696B2 Ordering of statistical correlated quantities 失效
标题翻译：统计相关数量的排序
公开(公告)号：US08510696B2
公开(公告)日：2013-08-13
申请号：US13422637
申请日：2012-03-16
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译：公布统计相关数量排序的解决方案。在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

6. 发明授权

US08266565B2 Ordering of statistical correlated quantities 有权
标题翻译：统计相关数量的排序
公开(公告)号：US08266565B2
公开(公告)日：2012-09-11
申请号：US12696186
申请日：2010-01-29
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译：公布统计相关数量排序的解决方案。在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

7. 发明申请

US20120192136A1 ORDERING OF STATISTICAL CORRELATED QUANTITIES 失效
标题翻译：统计相关数量的订购
公开(公告)号：US20120192136A1
公开(公告)日：2012-07-26
申请号：US13422637
申请日：2012-03-16
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
IPC分类号： G06F9/455
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译：公布统计相关数量排序的解决方案。在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

8. 发明申请

US20110191730A1 ORDERING OF STATISTICAL CORRELATED QUANTITIES 有权
标题翻译：统计相关数量的订购
公开(公告)号：US20110191730A1
公开(公告)日：2011-08-04
申请号：US12696186
申请日：2010-01-29
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译：公布统计相关数量排序的解决方案。在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式