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1. 发明授权

US5787008A Simulation corrected sensitivity 失效
标题翻译：模拟校正灵敏度
公开(公告)号：US5787008A
公开(公告)日：1998-07-28
申请号：US629488
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

2. 发明授权

US5790415A Complementary network reduction for load modeling 失效
标题翻译：用于负载建模的互补网络简化
公开(公告)号：US5790415A
公开(公告)日：1998-08-04
申请号：US630189
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

3. 发明授权

US5751593A Accurate delay prediction based on multi-model analysis 失效
标题翻译：基于多模型分析的精确延迟预测
公开(公告)号：US5751593A
公开(公告)日：1998-05-12
申请号：US629487
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于调整尺寸增加的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

4. 发明授权

US5903471A Method for optimizing element sizes in a semiconductor device 失效
标题翻译：用于优化半导体器件中的元件尺寸的方法
公开(公告)号：US5903471A
公开(公告)日：1999-05-11
申请号：US805862
申请日：1997-03-03
申请人： Satyamurthy Pullela , Timothy J. Edwards , Joseph Norton , Abhijit Dharchoudhury , David Blaauw
发明人： Satyamurthy Pullela , Timothy J. Edwards , Joseph Norton , Abhijit Dharchoudhury , David Blaauw
IPC分类号： H01L21/82 , G06F17/50 , G06F19/00
CPC分类号： G06F17/505
摘要： A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).
摘要翻译：对于电路中的每个节点（302）计算基于所需和实际延迟时间的松弛时间。对于电路中的每个元件，计算灵敏度（304）和品质因数（306）。对于计算出的品质因数确定方差（308）。当方差小于预定阈值（310,312）时，优化具有最小绝对值或优点的电路元件。

5. 发明授权

US07149674B1 Methods for analyzing integrated circuits and apparatus therefor 失效
标题翻译：用于分析集成电路的方法及其装置
公开(公告)号：US07149674B1
公开(公告)日：2006-12-12
申请号：US09580854
申请日：2000-05-30
申请人： Supamas Sirichotiyakul , David T. Blaauw , Timothy J. Edwards , Chanhee Oh , Rajendran V. Panda , Judah L. Adelman , David Moshe , Abhijit Dharchoudhury
发明人： Supamas Sirichotiyakul , David T. Blaauw , Timothy J. Edwards , Chanhee Oh , Rajendran V. Panda , Judah L. Adelman , David Moshe , Abhijit Dharchoudhury
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.
摘要翻译：公开了一种提高双电位集成电路性能的方法，其中针对具有第一阈值电压电平的集成电路的每个晶体管计算第一值。第一个值至少部分地基于如同对应的晶体管具有第二阈值电压电平那样计算的延迟和泄漏。然后基于第一值选择一个晶体管。然后将所选择的晶体管的阈值电压设置为第二阈值电压电平。电路内的至少一个晶体管的面积被修改，然后将电路的尺寸设定到预定区域。如果电路性能不能满足规定的约束，则可以重复该过程。在一个实施例中，性能确定包括计算电路被分配到其中的一组DC连接组件的漏电流，确定每个组件的主要逻辑状态，估计这些主要逻辑状态中的每一个的泄漏，以及求和基于状态概率的这些主成分的加权平均值。

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