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1. 发明授权

US07093223B2 Noise analysis for an integrated circuit model 有权
标题翻译：集成电路模型的噪声分析
公开(公告)号：US07093223B2
公开(公告)日：2006-08-15
申请号：US10304423
申请日：2002-11-26
申请人： Murat R. Becer , Ilan Algor , Rajendran V. Panda , David T. Blaauw
发明人： Murat R. Becer , Ilan Algor , Rajendran V. Panda , David T. Blaauw
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.
摘要翻译：一种减少串扰的设计和布线电路的方法。在全局路由（12）之后但在详细路由（28）之前执行早期噪声分析（22），以便在执行详细路由（28）之前修复问题（24）。在一个实施例中，早期噪声分析（22）之前是概率抽取（16）。在一个实施例中，概率提取（16）包括确定在预定的一组配置（54）中的每个配置的发生概率。然后进行概率电容提取（56）。使用提取的电容（60）构建概率分布耦合RC网络。在一个实施例中，概率提取（16）包括使用概率分布耦合RC网络估计攻击者强度（20）。

2. 发明授权

US07251797B2 Pessimism reduction in crosstalk noise aware static timing analysis 失效
标题翻译：串扰噪声感知静态时序分析的悲观主义减少
公开(公告)号：US07251797B2
公开(公告)日：2007-07-31
申请号：US10994858
申请日：2004-11-22
申请人： Murat R. Becer , Ilan Algor , Amir Grinshpon , Rafi Levy , Chanhee Oh , Rajendran V. Panda , Vladimir P. Zolotov
发明人： Murat R. Becer , Ilan Algor , Amir Grinshpon , Rafi Levy , Chanhee Oh , Rajendran V. Panda , Vladimir P. Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.
摘要翻译：用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何部分316对受害者时机的影响超出受害者定时窗口。有效的延迟时间用于调整受害者计时窗口。基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u 1）（613,625）。

3. 发明授权

US07149674B1 Methods for analyzing integrated circuits and apparatus therefor 失效
标题翻译：用于分析集成电路的方法及其装置
公开(公告)号：US07149674B1
公开(公告)日：2006-12-12
申请号：US09580854
申请日：2000-05-30
申请人： Supamas Sirichotiyakul , David T. Blaauw , Timothy J. Edwards , Chanhee Oh , Rajendran V. Panda , Judah L. Adelman , David Moshe , Abhijit Dharchoudhury
发明人： Supamas Sirichotiyakul , David T. Blaauw , Timothy J. Edwards , Chanhee Oh , Rajendran V. Panda , Judah L. Adelman , David Moshe , Abhijit Dharchoudhury
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.
摘要翻译：公开了一种提高双电位集成电路性能的方法，其中针对具有第一阈值电压电平的集成电路的每个晶体管计算第一值。第一个值至少部分地基于如同对应的晶体管具有第二阈值电压电平那样计算的延迟和泄漏。然后基于第一值选择一个晶体管。然后将所选择的晶体管的阈值电压设置为第二阈值电压电平。电路内的至少一个晶体管的面积被修改，然后将电路的尺寸设定到预定区域。如果电路性能不能满足规定的约束，则可以重复该过程。在一个实施例中，性能确定包括计算电路被分配到其中的一组DC连接组件的漏电流，确定每个组件的主要逻辑状态，估计这些主要逻辑状态中的每一个的泄漏，以及求和基于状态概率的这些主成分的加权平均值。

4. 发明授权

US06819538B2 Method and apparatus for controlling current demand in an integrated circuit 有权
标题翻译：用于控制集成电路中的电流需求的方法和装置
公开(公告)号：US06819538B2
公开(公告)日：2004-11-16
申请号：US09858126
申请日：2001-05-15
申请人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
发明人： David T. Blaauw , Rajendran V. Panda , Rajat Chaudhry , Vladimir P. Zolotov , Ravindraraj Ramaraju
IPC分类号： H02H300
CPC分类号： G06F1/305
摘要： The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.
摘要翻译：本发明一般涉及用于控制集成电路中的电流需求的方法和装置。一个实施例涉及一种方法，其包括检测是否存在电源电压过冲或下冲，并且如果检测到的话，控制消耗电力消耗的电流以确保电源电压保持在可接受的水平内。其他实施例涉及具有电容去耦结构，功耗电路和功耗控制电路的集成电路，用于控制由功耗电路的至少一部分消耗的电流。因此，本发明的实施例涉及监视和控制功耗电路（例如集成电路）的功耗（即电流需求），以便防止毁坏性的电源电压欠冲，过冲和振荡。

5. 发明授权

US07571404B2 Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise 有权
标题翻译：快速片上去耦电容预算方法和设备，用于降低电源噪声
公开(公告)号：US07571404B2
公开(公告)日：2009-08-04
申请号：US11566915
申请日：2006-12-05
申请人： Min Zhao , Rajendran V. Panda , Savithri Sundareswaran
发明人： Min Zhao , Rajendran V. Panda , Savithri Sundareswaran
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036 , G06F2217/78
摘要： A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the decap can be distributed throughout a hot spot region of the semiconductor circuit design and not be limited to placement at a single location in the circuit. Dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level.
摘要翻译：制定半导体电力网络去耦电容（decap）预算问题，以最小化在半导体电路设计的网络节点上受到电压约束的要添加到网络中的总斩波。考虑到要拆分的电压限制，使得可以将分拆分布在半导体电路设计的热点区域中，并且不限于放置在电路中的单个位置。动态网络电压始终保持大于用户指定的阈值电压电平。

6. 发明授权

US07127384B2 Fast simulation of circuitry having SOI transistors 失效
标题翻译：具有SOI晶体管的电路的快速仿真
公开(公告)号：US07127384B2
公开(公告)日：2006-10-24
申请号：US10333432
申请日：2002-08-27
申请人： Vladimir P. Zolotov , Rajendran V. Panda , Sergey V. Gavrilov , Alexey L. Glebov , Yury B. Egorov , Dmitry Y. Nadexhin
发明人： Vladimir P. Zolotov , Rajendran V. Panda , Sergey V. Gavrilov , Alexey L. Glebov , Yury B. Egorov , Dmitry Y. Nadexhin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022
摘要： A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.
摘要翻译： SOI MOS电路的快速瞬态模拟器使用快速准确的SOI晶体管表模型。模拟器使用具有分区的电路的表示。通过数值求解描述其瞬态行为的微分方程，每个分区通过简单的时间步长分别进行模拟。以事件驱动的方式模拟整个电路的行为，其中每个事件对应于每个分区的积分时间步长。代替体电压，模拟器实现了一种变换，并将身体电荷作为一个独立的变量，以获得高精度和高速度的模拟。 SOI晶体管表模型的构建导致速度和精度的提高。该转换允许通过SOI晶体管背栅极电容近似恒定的事实减少表尺寸数量。

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