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1. 发明授权

US5787008A Simulation corrected sensitivity 失效
标题翻译：模拟校正灵敏度
公开(公告)号：US5787008A
公开(公告)日：1998-07-28
申请号：US629488
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton , Peter R. O'Brien
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

2. 发明授权

US5790415A Complementary network reduction for load modeling 失效
标题翻译：用于负载建模的互补网络简化
公开(公告)号：US5790415A
公开(公告)日：1998-08-04
申请号：US630189
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于尺寸增加（415）的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

3. 发明授权

US5751593A Accurate delay prediction based on multi-model analysis 失效
标题翻译：基于多模型分析的精确延迟预测
公开(公告)号：US5751593A
公开(公告)日：1998-05-12
申请号：US629487
申请日：1996-04-10
申请人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
发明人： Satyamurthy Pullela , Abhijit Dharchoudhury , David T. Blaauw , Tim J. Edwards , Joseph W. Norton
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.
摘要翻译：用于最佳地确定集成电路元件的尺寸的过程和实现计算机系统（13）包括确定集成电路内所有节点处的处理信号的实际到达时间和所需的到达时间（403），并确定到达之间的松弛或差异（405）和每个节点所需的时间。如果特定节点的实际到达时间在满足节点（407）的预定设计约束所需的时间之后，则确定（411）关于该元素对节点松弛的影响，以增加节点该元素的大小。此后，根据加权函数选择用于调整尺寸增加的元件（413），并重复该过程，直到集成电路中的所有节点具有正的松弛时间（407,409）。实现定时分析步骤（303）的一种方法包括一种分析电路仿真技术（1000-1015），其中电路“IV”特性被更精确地用包括多个区域分段近似（901- 907）。定时分析的另一种方法包括将无源晶体管转换为等效RC网络的等效方法（1501-1513）（801）。在整体优化过程中，提供了一种基于校正因子（1713）自动校正晶体管预测灵敏度的方法（1701-1715）。还示出了多模式定时方法（1601-1619）（1601-1619），用于协同地组合快速和精确的电路定时模型，以优化设计过程本身的速度和精度，同时保持在精度阈值内。

4. 发明授权

US5506728A Dual combiner eyepiece 失效
标题翻译：双组合目镜
公开(公告)号：US5506728A
公开(公告)日：1996-04-09
申请号：US258412
申请日：1994-06-10
申请人： Tim J. Edwards , Mayer Rud
发明人： Tim J. Edwards , Mayer Rud
IPC分类号： G02B25/00 , G02B27/14
CPC分类号： G02B25/001
摘要： A combiner eyepiece with an enhancement imagery source and a collimating mirror is equipped with two oblique partially reflective mirrors. Both mirrors reflect some of the light impinging on their partially reflective sides and transmit substantially all of the rest of such light. The result is a collimated beam of light travelling toward the viewer along the viewing axis and expanded in vertical extent. This expanded vertical extent eases the requirement for the viewer to place his eyes in a precise location at the near end of the eyepiece. It also allows a smaller and lighter construction for an eyepiece where the vertical extent of the viewing area has been specified.
摘要翻译：具有增强图像源和准直镜的组合器目镜配备有两个倾斜的部分反射镜。两个反射镜都反映了一些入射到它们的部分反射面上的光并且基本上传播了其余所有的光。结果是沿着观察轴向观察者行进的准直光束并且在垂直方向上扩展。这种扩大的垂直范围减轻了观众将眼睛放在目镜近端的精确位置的要求。它还允许在已经指定了观察区域的垂直范围的情况下用于目镜的较小和较轻的结构。

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