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1. 发明授权

US08140923B2 Test circuit and method for testing of infant mortality related defects 失效
标题翻译：用于测试婴儿死亡率相关缺陷的测试电路和方法
公开(公告)号：US08140923B2
公开(公告)日：2012-03-20
申请号：US12421527
申请日：2009-04-09
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
IPC分类号： G01R31/28 , G01R35/00 , G01R31/00
CPC分类号： G01R31/31922 , G01R31/3016
摘要： The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.
摘要翻译：本公开提供了IC的实施例和测试IC的方法。在一个实施例中，IC包括：（1）具有节点和至少一个顺序逻辑元件的功能逻辑路径和（2）耦合到功能逻辑路径并具有延迟块的测试电路，所述测试电路被配置为形成响应于测试模式信号包括延迟块和节点的可测试路径，其中选择延迟块的延迟值以检测与该节点相关联的小延迟缺陷。

2. 发明授权

US08515695B2 Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC 失效
标题翻译：用于评估在IC上设置的测试图案的小延迟缺陷覆盖的方法和装置
公开(公告)号：US08515695B2
公开(公告)日：2013-08-20
申请号：US12421481
申请日：2009-04-09
申请人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
发明人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
IPC分类号： G01R31/3181
CPC分类号： G01R31/31835
摘要： A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.
摘要翻译：公开了一种用于评估测试图案组的SDDC的方法和装置。在一个实施例中，该方法包括：（1）选择由测试模式组检测到的IC的转换故障，在IC的故障位置发生的转换故障，（2）识别最长可测试路径的路径延迟和 IC的最长测试路径，其中最长可测试路径和最长测试路径都包括故障位置，（3）基于SDD将会发生的概率来确定最长可测试路径和最长测试路径的SDD检测概率（4）通过将最长测试路径的SDD检测概率除以最长可测试路径的SDD检测概率，计算出转换故障的SDDC。

3. 发明授权

US08352818B2 Method for generating test patterns for small delay defects 失效
标题翻译：用于生成小延迟缺陷的测试模式的方法
公开(公告)号：US08352818B2
公开(公告)日：2013-01-08
申请号：US12336472
申请日：2008-12-16
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328
摘要： A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
摘要翻译：公开了一种用于产生用于检测IC的小延迟缺陷的测试图案集的方法。在一个实施例中，该方法包括：（1）产生传统的延迟故障模式，（2）对小延迟缺陷覆盖的传统延迟故障模式进行故障分级，（3）报告故障等级检测到的故障和与检测到的故障，（4）确定哪个检测到的故障是采用延迟信息的定时感知目标故障，以及（5）为定时感知目标故障产生定时感知延迟故障模式。

4. 发明申请

US20100153795A1 METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS 失效
标题翻译：用于生成小延迟缺陷的测试模式的方法
公开(公告)号：US20100153795A1
公开(公告)日：2010-06-17
申请号：US12336472
申请日：2008-12-16
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
IPC分类号： G06F11/16
CPC分类号： G01R31/318328
摘要： A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
摘要翻译：公开了一种用于产生用于检测IC的小延迟缺陷的测试图案集的方法。在一个实施例中，该方法包括：（1）产生传统的延迟故障模式，（2）对小延迟缺陷覆盖的传统延迟故障模式进行故障分级，（3）报告故障等级检测到的故障和与检测到的故障，（4）确定哪个检测到的故障是采用延迟信息的定时感知目标故障，以及（5）为定时感知目标故障产生定时感知延迟故障模式。

5. 发明申请

US20100262876A1 TEST CIRCUIT AND METHOD FOR TESTING OF INFANT MORTALITY RELATED DEFECTS 失效
标题翻译：测试电路和测试婴儿死亡相关缺陷的方法
公开(公告)号：US20100262876A1
公开(公告)日：2010-10-14
申请号：US12421527
申请日：2009-04-09
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31922 , G01R31/3016
摘要： The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.
摘要翻译：本公开提供了IC的实施例和测试IC的方法。在一个实施例中，IC包括：（1）具有节点和至少一个顺序逻辑元件的功能逻辑路径和（2）耦合到功能逻辑路径并具有延迟块的测试电路，所述测试电路被配置为形成响应于测试模式信号包括延迟块和节点的可测试路径，其中选择延迟块的延迟值以检测与该节点相关联的小延迟缺陷。

6. 发明申请

US20100262394A1 METHOD AND AN APPARATUS FOR EVALUATING SMALL DELAY DEFECT COVERAGE OF A TEST PATTERN SET ON AN IC 失效
标题翻译：用于评估IC上测试图案的小延迟缺陷覆盖的方法和装置
公开(公告)号：US20100262394A1
公开(公告)日：2010-10-14
申请号：US12421481
申请日：2009-04-09
申请人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
发明人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
IPC分类号： G06F19/00 , G01R29/00
CPC分类号： G01R31/31835
摘要： A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.
摘要翻译：公开了一种用于评估测试图案组的SDDC的方法和装置。在一个实施例中，该方法包括：（1）选择由测试模式组检测到的IC的转换故障，在IC的故障位置发生的转换故障，（2）识别最长可测试路径的路径延迟和 IC的最长测试路径，其中最长可测试路径和最长测试路径都包括故障位置，（3）基于SDD将会发生的概率来确定最长可测试路径和最长测试路径的SDD检测概率（4）通过将最长测试路径的SDD检测概率除以最长可测试路径的SDD检测概率，计算出转换故障的SDDC。

7. 发明授权

US09704766B2 Interposers of 3-dimensional integrated circuit package systems and methods of designing the same 有权
公开(公告)号：US09704766B2
公开(公告)日：2017-07-11
申请号：US13118201
申请日：2011-05-27
申请人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
发明人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
IPC分类号： H01L23/48 , H01L21/66 , H01L25/065
CPC分类号： H01L22/32 , H01L25/0655 , H01L2224/16225 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/00
摘要： An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

8. 发明授权

US09041411B2 Testing of an integrated circuit that contains secret information 有权
标题翻译：测试包含秘密信息的集成电路
公开(公告)号：US09041411B2
公开(公告)日：2015-05-26
申请号：US12063151
申请日：2006-08-09
申请人： Erik J. Marinissen , Sandeep Kumar Goel , Andre K. Nieuwland , Hubertus G. H. Vermuelen , Hendrikus P. E. Vranken
发明人： Erik J. Marinissen , Sandeep Kumar Goel , Andre K. Nieuwland , Hubertus G. H. Vermuelen , Hendrikus P. E. Vranken
IPC分类号： G01R31/02 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31719 , G01R31/318533
摘要： An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown. As a result, a person that does not know which fuse elements are first fuse elements and which are second fuse elements is presented with difficulties to restore the integrated circuit to a state where test access with the danger of access to the secured information is possible.
摘要翻译：集成电路（10）包括功能电路（12a-c），其包含必须防止未授权访问的信息。集成电路包括耦合到功能电路（12a-c）的测试访问电路（14,16）和耦合到测试访问电路（14,16）的多个熔丝元件（18）。保险丝元件（18）以仅在多个第一熔丝元件（18）处于吹制状态时通过测试存取电路（14,16）可一致地访问的电路配置连接并且多个的第二熔丝元件（18）处于未吹塑状态。结果，可以在选择性地吹扫所有第一熔丝元件（18）之后测试集成电路。在测试之后，至少部分第二熔丝元件（18）被吹塑。结果，不知道哪些熔丝元件是第一熔丝元件并且是第二熔丝元件的人被呈现难以将集成电路恢复到具有访问安全信息的危险的测试访问是可能的状态。

9. 发明授权

US08972918B2 System and method for functional verification of multi-die 3D ICs 有权
标题翻译：多芯片3D IC的功能验证系统和方法
公开(公告)号：US08972918B2
公开(公告)日：2015-03-03
申请号：US13359921
申请日：2012-01-27
申请人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G01R31/2886 , G01R31/318513
摘要： A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
摘要翻译：公开了一种用于多芯片3D IC的功能验证的系统和方法。该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

10. 发明授权

US08914692B2 DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips 有权
标题翻译：用于宽I / O DRAM的2.5D / 3D系统芯片的DRAM测试架构
公开(公告)号：US08914692B2
公开(公告)日：2014-12-16
申请号：US13484729
申请日：2012-05-31
申请人： Sandeep Kumar Goel
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/28 , G11C29/56 , G11C11/40
CPC分类号： G11C29/56 , G11C11/40 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
摘要翻译： 2.5D或3D测试架构包括一个逻辑管芯和一个内存管芯。在2.5D架构中，逻辑管芯和存储器管芯安装在插入器上。在3D架构中，存储器管芯安装在逻辑管芯上。逻辑管芯包括用处理器封装件封装的控制逻辑。处理器包装器可以测试控制逻辑的组件。存储器管芯也安装在插入器上。存储器管芯包括动态随机存取存储器和通道选择/旁路逻辑。控制逻辑经由信道选择/旁路逻辑耦合到动态随机存取存储器，信道选择/旁路逻辑由处理器封装器控制。

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