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1. 发明授权

US08140923B2 Test circuit and method for testing of infant mortality related defects 失效
标题翻译：用于测试婴儿死亡率相关缺陷的测试电路和方法
公开(公告)号：US08140923B2
公开(公告)日：2012-03-20
申请号：US12421527
申请日：2009-04-09
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
IPC分类号： G01R31/28 , G01R35/00 , G01R31/00
CPC分类号： G01R31/31922 , G01R31/3016
摘要： The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.
摘要翻译：本公开提供了IC的实施例和测试IC的方法。在一个实施例中，IC包括：（1）具有节点和至少一个顺序逻辑元件的功能逻辑路径和（2）耦合到功能逻辑路径并具有延迟块的测试电路，所述测试电路被配置为形成响应于测试模式信号包括延迟块和节点的可测试路径，其中选择延迟块的延迟值以检测与该节点相关联的小延迟缺陷。

2. 发明申请

US20100262876A1 TEST CIRCUIT AND METHOD FOR TESTING OF INFANT MORTALITY RELATED DEFECTS 失效
标题翻译：测试电路和测试婴儿死亡相关缺陷的方法
公开(公告)号：US20100262876A1
公开(公告)日：2010-10-14
申请号：US12421527
申请日：2009-04-09
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31922 , G01R31/3016
摘要： The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.
摘要翻译：本公开提供了IC的实施例和测试IC的方法。在一个实施例中，IC包括：（1）具有节点和至少一个顺序逻辑元件的功能逻辑路径和（2）耦合到功能逻辑路径并具有延迟块的测试电路，所述测试电路被配置为形成响应于测试模式信号包括延迟块和节点的可测试路径，其中选择延迟块的延迟值以检测与该节点相关联的小延迟缺陷。

3. 发明申请

US20100262394A1 METHOD AND AN APPARATUS FOR EVALUATING SMALL DELAY DEFECT COVERAGE OF A TEST PATTERN SET ON AN IC 失效
标题翻译：用于评估IC上测试图案的小延迟缺陷覆盖的方法和装置
公开(公告)号：US20100262394A1
公开(公告)日：2010-10-14
申请号：US12421481
申请日：2009-04-09
申请人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
发明人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
IPC分类号： G06F19/00 , G01R29/00
CPC分类号： G01R31/31835
摘要： A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.
摘要翻译：公开了一种用于评估测试图案组的SDDC的方法和装置。在一个实施例中，该方法包括：（1）选择由测试模式组检测到的IC的转换故障，在IC的故障位置发生的转换故障，（2）识别最长可测试路径的路径延迟和 IC的最长测试路径，其中最长可测试路径和最长测试路径都包括故障位置，（3）基于SDD将会发生的概率来确定最长可测试路径和最长测试路径的SDD检测概率（4）通过将最长测试路径的SDD检测概率除以最长可测试路径的SDD检测概率，计算出转换故障的SDDC。

4. 发明授权

US08515695B2 Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC 失效
标题翻译：用于评估在IC上设置的测试图案的小延迟缺陷覆盖的方法和装置
公开(公告)号：US08515695B2
公开(公告)日：2013-08-20
申请号：US12421481
申请日：2009-04-09
申请人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
发明人： Narendra B. Devta-Prasanna , Sandeep Kumar Goel
IPC分类号： G01R31/3181
CPC分类号： G01R31/31835
摘要： A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.
摘要翻译：公开了一种用于评估测试图案组的SDDC的方法和装置。在一个实施例中，该方法包括：（1）选择由测试模式组检测到的IC的转换故障，在IC的故障位置发生的转换故障，（2）识别最长可测试路径的路径延迟和 IC的最长测试路径，其中最长可测试路径和最长测试路径都包括故障位置，（3）基于SDD将会发生的概率来确定最长可测试路径和最长测试路径的SDD检测概率（4）通过将最长测试路径的SDD检测概率除以最长可测试路径的SDD检测概率，计算出转换故障的SDDC。

5. 发明授权

US08352818B2 Method for generating test patterns for small delay defects 失效
标题翻译：用于生成小延迟缺陷的测试模式的方法
公开(公告)号：US08352818B2
公开(公告)日：2013-01-08
申请号：US12336472
申请日：2008-12-16
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328
摘要： A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
摘要翻译：公开了一种用于产生用于检测IC的小延迟缺陷的测试图案集的方法。在一个实施例中，该方法包括：（1）产生传统的延迟故障模式，（2）对小延迟缺陷覆盖的传统延迟故障模式进行故障分级，（3）报告故障等级检测到的故障和与检测到的故障，（4）确定哪个检测到的故障是采用延迟信息的定时感知目标故障，以及（5）为定时感知目标故障产生定时感知延迟故障模式。

6. 发明申请

US20100153795A1 METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS 失效
标题翻译：用于生成小延迟缺陷的测试模式的方法
公开(公告)号：US20100153795A1
公开(公告)日：2010-06-17
申请号：US12336472
申请日：2008-12-16
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
IPC分类号： G06F11/16
CPC分类号： G01R31/318328
摘要： A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
摘要翻译：公开了一种用于产生用于检测IC的小延迟缺陷的测试图案集的方法。在一个实施例中，该方法包括：（1）产生传统的延迟故障模式，（2）对小延迟缺陷覆盖的传统延迟故障模式进行故障分级，（3）报告故障等级检测到的故障和与检测到的故障，（4）确定哪个检测到的故障是采用延迟信息的定时感知目标故障，以及（5）为定时感知目标故障产生定时感知延迟故障模式。

7. 发明授权

US08412994B2 Design-for-test technique to reduce test volume including a clock gate controller 有权
标题翻译：设计测试技术，以减少测试体积，包括时钟门控制器
公开(公告)号：US08412994B2
公开(公告)日：2013-04-02
申请号：US12885153
申请日：2010-09-17
申请人： Narendra B. Devta-Prasanna
发明人： Narendra B. Devta-Prasanna
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318544
摘要： Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.
摘要翻译：提供了集成电路的时钟控制电路，测试具有时钟门的集成电路的方法，集成电路和包括时钟控制电路的单元库。在一个实施例中，集成电路包括：（1）时钟门，被配置为将时钟信号施加到集成电路的至少第一扫描链，（2）耦合到时钟门的输入的组合逻辑，以及（3）设计测试逻辑，位于组合逻辑的外部，并耦合到时钟门和集成电路的第二扫描链的第一单元，该被测设计设计逻辑被配置为基于第一个单元格的逻辑值。

8. 发明申请

US20120072797A1 DESIGN-FOR-TEST TECHNIQUE TO REDUCE TEST VOLUME INCLUDING A CLOCK GATE CONTROLLER 有权
标题翻译：降低测试音量的设计测试技术，包括时钟控制器
公开(公告)号：US20120072797A1
公开(公告)日：2012-03-22
申请号：US12885153
申请日：2010-09-17
申请人： Narendra B. Devta-Prasanna
发明人： Narendra B. Devta-Prasanna
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318594 , G01R31/318544
摘要： Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.
摘要翻译：提供了集成电路的时钟控制电路，测试具有时钟门的集成电路的方法，集成电路和包括时钟控制电路的单元库。在一个实施例中，集成电路包括：（1）时钟门，被配置为将时钟信号施加到集成电路的至少第一扫描链，（2）耦合到时钟门的输入的组合逻辑，以及（3）设计测试逻辑，位于组合逻辑的外部，并耦合到时钟门和集成电路的第二扫描链的第一单元，该被测设计设计逻辑被配置为基于第一个单元格的逻辑值。

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