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1. 发明授权

US09704766B2 Interposers of 3-dimensional integrated circuit package systems and methods of designing the same 有权
公开(公告)号：US09704766B2
公开(公告)日：2017-07-11
申请号：US13118201
申请日：2011-05-27
申请人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
发明人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
IPC分类号： H01L23/48 , H01L21/66 , H01L25/065
CPC分类号： H01L22/32 , H01L25/0655 , H01L2224/16225 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/00
摘要： An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

2. 发明授权

US09817029B2 Test probing structure 有权
公开(公告)号：US09817029B2
公开(公告)日：2017-11-14
申请号：US13313228
申请日：2011-12-07
申请人： Mill-Jer Wang , Ching-Fang Chen , Sandeep Kumar Goel , Chung-Sheng Yuan , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee , Hung-Chih Lin
发明人： Mill-Jer Wang , Ching-Fang Chen , Sandeep Kumar Goel , Chung-Sheng Yuan , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee , Hung-Chih Lin
IPC分类号： G01R1/067 , G01R1/073
CPC分类号： G01R1/07342 , G01R1/07378 , H01L2224/16225
摘要： A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

3. 发明授权

US08707238B2 Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs 有权
标题翻译：确定最佳微型凸点探针焊盘配对的方法，用于插入器设计中的高效PGD测试
公开(公告)号：US08707238B2
公开(公告)日：2014-04-22
申请号：US13484531
申请日：2012-05-31
申请人： Yi-Lin Chuang , Cheng-Pin Chiu , Ching-Fang Chen , Ji-Jan Chen , Sandeep Kumar Goel , Yun-Han Lee , Charles C. C. Liu
发明人： Yi-Lin Chuang , Cheng-Pin Chiu , Ching-Fang Chen , Ji-Jan Chen , Sandeep Kumar Goel , Yun-Han Lee , Charles C. C. Liu
IPC分类号： G06F17/50
CPC分类号： G01R31/2889
摘要： The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.
摘要翻译：本公开涉及一种将探针焊盘布置到插入件的微凸块的方法。提供具有目标微凸块和探针垫的插入件。探针垫最初未分配。获得目标微凸点位置和探针垫位置。获得从探针焊盘到目标微凸块的可能路线分配。至少部分地根据目标微凸块位置和探针垫位置为可能的路线分配开发成本。根据成本从可能的分配中选择最终作业。

4. 发明授权

US08860448B2 Test schemes and apparatus for passive interposers 有权
标题翻译：被动中介器的测试方案和设备
公开(公告)号：US08860448B2
公开(公告)日：2014-10-14
申请号：US13184008
申请日：2011-07-15
申请人： Yun-Han Lee , Mill-Jer Wang , Tan-Li Chou
发明人： Yun-Han Lee , Mill-Jer Wang , Tan-Li Chou
IPC分类号： G01R31/20 , G01R1/073
CPC分类号： G01R1/07385
摘要： A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.
摘要翻译：探针卡包括多个探针，以及连接到多个探针的开关网络。开关网络被配置为以第一模式连接多个探针，并且以与第一图案不同的第二图案重新连接多个探针。

5. 发明申请

US20130326463A1 Method to Determine Optimal Micro-Bump-Probe Pad Pairing for Efficient PGD Testing in Interposer Designs 有权
标题翻译：确定内插器设计中高效PGD测试的最佳微型碰撞探针焊盘配对的方法
公开(公告)号：US20130326463A1
公开(公告)日：2013-12-05
申请号：US13484531
申请日：2012-05-31
申请人： Yi-Lin Chuang , Cheng-Pin Chiu , Ching-Fang Chen , Ji-Jan Chen , Sandeep Kumar Goel , Yun-Han Lee , Charles C.C. Liu
发明人： Yi-Lin Chuang , Cheng-Pin Chiu , Ching-Fang Chen , Ji-Jan Chen , Sandeep Kumar Goel , Yun-Han Lee , Charles C.C. Liu
IPC分类号： G06F17/50
CPC分类号： G01R31/2889
摘要： The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.
摘要翻译：本公开涉及一种将探针焊盘布置到插入件的微凸块的方法。提供具有目标微凸块和探针垫的插入件。探针垫最初未分配。获得目标微凸点位置和探针垫位置。获得从探针焊盘到目标微凸块的可能路线分配。至少部分地根据目标微凸块位置和探针垫位置为可能的路线分配开发成本。根据成本从可能的分配中选择最终作业。

6. 发明申请

US20130015872A1 Test Schemes and Apparatus for Passive Interposers 有权
标题翻译：被动介质的测试方案和设备
公开(公告)号：US20130015872A1
公开(公告)日：2013-01-17
申请号：US13184008
申请日：2011-07-15
申请人： Yun-Han Lee , Mill-Jer Wang , Tan-Li Chou
发明人： Yun-Han Lee , Mill-Jer Wang , Tan-Li Chou
IPC分类号： G01R1/073 , G01R31/20
CPC分类号： G01R1/07385
摘要： A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.
摘要翻译：探针卡包括多个探针，以及连接到多个探针的开关网络。开关网络被配置为以第一模式连接多个探针，并且以与第一图案不同的第二图案重新连接多个探针。

7. 发明申请

US20140075404A1 GROUP BOUNDING BOX REGION-CONSTRAINED PLACEMENT FOR INTEGRATED CIRCUIT DESIGN 有权
标题翻译：集成电路设计的组接线盒区域约束放置
公开(公告)号：US20140075404A1
公开(公告)日：2014-03-13
申请号：US13613678
申请日：2012-09-13
申请人： Yi-Lin Chuang , Chun-Cheng Ku , Yun-Han Lee , Shao-Yu Wang , Wei-Pin Changchien , Chin-Chou Liu
发明人： Yi-Lin Chuang , Chun-Cheng Ku , Yun-Han Lee , Shao-Yu Wang , Wei-Pin Changchien , Chin-Chou Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.
摘要翻译：除此之外，本文提供了一种或多种用于定义用于集成电路的相关单元的组边界框以及为包括组边界框的集成电路生成新布局的系统和技术。也就是说，基于相关单元的位置值来定义一个或多个组边界框。基于诸如考虑线长度，定时和单元密度的目标函数的放置技术，将这样的组边界框放置在新布局内。一个或多个组边界框的大小或重新形状以减少新布局中的单元格重叠。以这种方式，新布局包括根据减轻集成电路的线长度和定时延迟的配置放置在新布局内的由一个或多个组边界框绑定的相关单元。

8. 发明授权

US08113412B1 Methods for detecting defect connections between metal bumps 有权
标题翻译：检测金属凸块之间缺陷连接的方法
公开(公告)号：US08113412B1
公开(公告)日：2012-02-14
申请号：US13107476
申请日：2011-05-13
申请人： Nan-Hsin Tseng , Yun-Han Lee , Chin-Chou Liu , Ji-Jan Chen , Wei-Pin Changchien , Chien-Hui Chen
发明人： Nan-Hsin Tseng , Yun-Han Lee , Chin-Chou Liu , Ji-Jan Chen , Wei-Pin Changchien , Chien-Hui Chen
IPC分类号： B23K31/02 , B23K31/12
CPC分类号： G01R31/2853 , G01R31/307
摘要： A method includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.
摘要翻译：一种方法包括将互连部件的第一表面上的第一多个金属凸块电接地到公共接地板。产生互连部件的第二多个金属凸块的电压对比度（VC）图像。分析VC图像中的第二多个金属凸块的灰度级，以发现第二多个金属凸块和第一多个金属凸块中的相应的金属凸块之间的缺陷连接。

9. 发明授权

US08701070B2 Group bounding box region-constrained placement for integrated circuit design 有权
标题翻译：集成电路设计的边界区域约束布局
公开(公告)号：US08701070B2
公开(公告)日：2014-04-15
申请号：US13613678
申请日：2012-09-13
申请人： Yi-Lin Chuang , Chun-Cheng Ku , Yun-Han Lee , Shao-Yu Wang , Wei-Pin Changchien , Chin-Chou Liu
发明人： Yi-Lin Chuang , Chun-Cheng Ku , Yun-Han Lee , Shao-Yu Wang , Wei-Pin Changchien , Chin-Chou Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.
摘要翻译：除此之外，本文提供了一种或多种用于定义用于集成电路的相关单元的组边界框并且为包括组边界框的集成电路生成新布局的系统和技术。也就是说，基于相关单元的位置值来定义一个或多个组边界框。基于诸如考虑线长度，定时和单元密度的目标函数的放置技术，将这样的组边界框放置在新布局内。一个或多个组边界框的大小或重新形状以减少新布局中的单元格重叠。以这种方式，新布局包括根据减轻集成电路的线长度和定时延迟的配置放置在新布局内的由一个或多个组边界框绑定的相关单元。

10. 发明授权

US08276110B2 Reducing voltage drops in power networks using unused spaces in integrated circuits 有权
标题翻译：降低集成电路中未使用空间的电力网络中的电压降
公开(公告)号：US08276110B2
公开(公告)日：2012-09-25
申请号：US12692184
申请日：2010-01-22
申请人： Dinesh Baviskar , Wen-Hao Chen , Chung-Sheng Yuan , Mark Shane Peng , Yun-Han Lee
发明人： Dinesh Baviskar , Wen-Hao Chen , Chung-Sheng Yuan , Mark Shane Peng , Yun-Han Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78
摘要： A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
摘要翻译：设计集成电路的方法包括提供包括电力网络的集成电路设计。提供一种电压降缓解系统，其包括被配置为在电力网络中自动找到源节点和终端节点的电力带增强器。添加了使用电压降缓解系统的用于电力网络的冗余带，其中冗余带将源节点和终端节点互连。在添加冗余带的步骤之后，可以添加虚拟图案。

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