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1. 发明授权

US09041411B2 Testing of an integrated circuit that contains secret information 有权
标题翻译：测试包含秘密信息的集成电路
公开(公告)号：US09041411B2
公开(公告)日：2015-05-26
申请号：US12063151
申请日：2006-08-09
申请人： Erik J. Marinissen , Sandeep Kumar Goel , Andre K. Nieuwland , Hubertus G. H. Vermuelen , Hendrikus P. E. Vranken
发明人： Erik J. Marinissen , Sandeep Kumar Goel , Andre K. Nieuwland , Hubertus G. H. Vermuelen , Hendrikus P. E. Vranken
IPC分类号： G01R31/02 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31719 , G01R31/318533
摘要： An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown. As a result, a person that does not know which fuse elements are first fuse elements and which are second fuse elements is presented with difficulties to restore the integrated circuit to a state where test access with the danger of access to the secured information is possible.
摘要翻译：集成电路（10）包括功能电路（12a-c），其包含必须防止未授权访问的信息。集成电路包括耦合到功能电路（12a-c）的测试访问电路（14,16）和耦合到测试访问电路（14,16）的多个熔丝元件（18）。保险丝元件（18）以仅在多个第一熔丝元件（18）处于吹制状态时通过测试存取电路（14,16）可一致地访问的电路配置连接并且多个的第二熔丝元件（18）处于未吹塑状态。结果，可以在选择性地吹扫所有第一熔丝元件（18）之后测试集成电路。在测试之后，至少部分第二熔丝元件（18）被吹塑。结果，不知道哪些熔丝元件是第一熔丝元件并且是第二熔丝元件的人被呈现难以将集成电路恢复到具有访问安全信息的危险的测试访问是可能的状态。

2. 发明授权

US09704766B2 Interposers of 3-dimensional integrated circuit package systems and methods of designing the same 有权
公开(公告)号：US09704766B2
公开(公告)日：2017-07-11
申请号：US13118201
申请日：2011-05-27
申请人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
发明人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
IPC分类号： H01L23/48 , H01L21/66 , H01L25/065
CPC分类号： H01L22/32 , H01L25/0655 , H01L2224/16225 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/00
摘要： An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

3. 发明授权

US08972918B2 System and method for functional verification of multi-die 3D ICs 有权
标题翻译：多芯片3D IC的功能验证系统和方法
公开(公告)号：US08972918B2
公开(公告)日：2015-03-03
申请号：US13359921
申请日：2012-01-27
申请人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G01R31/2886 , G01R31/318513
摘要： A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
摘要翻译：公开了一种用于多芯片3D IC的功能验证的系统和方法。该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

4. 发明授权

US08914692B2 DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips 有权
标题翻译：用于宽I / O DRAM的2.5D / 3D系统芯片的DRAM测试架构
公开(公告)号：US08914692B2
公开(公告)日：2014-12-16
申请号：US13484729
申请日：2012-05-31
申请人： Sandeep Kumar Goel
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/28 , G11C29/56 , G11C11/40
CPC分类号： G11C29/56 , G11C11/40 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
摘要翻译： 2.5D或3D测试架构包括一个逻辑管芯和一个内存管芯。在2.5D架构中，逻辑管芯和存储器管芯安装在插入器上。在3D架构中，存储器管芯安装在逻辑管芯上。逻辑管芯包括用处理器封装件封装的控制逻辑。处理器包装器可以测试控制逻辑的组件。存储器管芯也安装在插入器上。存储器管芯包括动态随机存取存储器和通道选择/旁路逻辑。控制逻辑经由信道选择/旁路逻辑耦合到动态随机存取存储器，信道选择/旁路逻辑由处理器封装器控制。

5. 发明授权

US08627160B2 System and device for reducing instantaneous voltage droop during a scan shift operation 有权
标题翻译：用于在扫描移位操作期间降低瞬时电压下降的系统和装置
公开(公告)号：US08627160B2
公开(公告)日：2014-01-07
申请号：US12727241
申请日：2010-04-21
申请人： Narendra Devta-Prasanna , Sandeep Kumar Goel , Arun K Gunda
发明人： Narendra Devta-Prasanna , Sandeep Kumar Goel , Arun K Gunda
IPC分类号： G01R31/28
CPC分类号： H03K3/015 , G01R31/318552 , G01R31/318594
摘要： A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.
摘要翻译：一种用于在扫描移位操作期间降低瞬时电压下降（IVD）的系统和装置。在一个实施例中，系统包括被配置为接收输入时钟信号的第一组时钟门控单元和耦合到第一组时钟门控单元的第一组触发器。第一组时钟门控单元的每个时钟选通单元包括第一延迟元件，用于在扫描移位操作期间将输入时钟信号延迟第一持续时间。该系统还包括被配置为接收输入时钟信号的第二组时钟门控单元，以及耦合到第二组时钟门控单元的第二组触发器。第二组时钟门控单元的每个时钟门控单元包括第二延迟单元，用于在扫描移位操作期间将输入时钟信号延迟第二持续时间。

6. 发明授权

US08566657B2 Circuit and method for diagnosing scan chain failures 有权
标题翻译：用于诊断扫描链失败的电路和方法
公开(公告)号：US08566657B2
公开(公告)日：2013-10-22
申请号：US13093942
申请日：2011-04-26
申请人： Sandeep Kumar Goel
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318561
摘要： A method includes shifting a first logic sequence into a first scan chain having a first plurality of scan blocks coupled together, outputting a second logic sequence from each of the plurality of scan blocks in the first scan chain to a respective scan block in a second scan chain, and shifting a third logic sequence out of the second scan chain. At least one improperly functioning scan block of the first scan chain is identified based on the third logic sequence shifted out of the second scan chain.
摘要翻译：一种方法包括将第一逻辑序列移动到具有耦合在一起的第一多个扫描块的第一扫描链中，将第一扫描链中的多个扫描块中的每一个的第二逻辑序列输出到第二扫描中的相应扫描块并且将第三逻辑序列移出第二扫描链。基于从第二扫描链中移出的第三逻辑序列来识别第一扫描链的至少一个不正常功能的扫描块。

7. 发明申请

US20120242367A1 CIRCUITS AND METHODS FOR TESTING THROUGH-SILICON VIAS 有权
标题翻译：用于测试硅橡胶的电路和方法
公开(公告)号：US20120242367A1
公开(公告)日：2012-09-27
申请号：US13053333
申请日：2011-03-22
申请人： Sandeep Kumar Goel
发明人： Sandeep Kumar Goel
IPC分类号： H03K19/003 , G01R31/02 , H03K19/173
CPC分类号： G01R1/07378 , G01R31/31855 , G01R31/318555 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during assembly comprises testing for short circuits and then exposing and connecting the TSVs via a conductive layer to check for open circuits.
摘要翻译：多级集成电路在包括TSV的多条信号线中的每一条上使用贯穿硅通孔（TSV）和时钟触发器之间相反方向的单独使能的缓冲器阵列。向TSV和相关触发器施加和/或读取逻辑电平产生逻辑元件与表征标称操作的预期值相比较或检测开路和短路缺陷的值。在组装期间测试TSV的过程包括测试短路，然后通过导电层暴露和连接TSV以检查开路。

8. 发明申请

US20120112763A1 Method for Detecting Small Delay Defects 有权
标题翻译：检测小延迟缺陷的方法
公开(公告)号：US20120112763A1
公开(公告)日：2012-05-10
申请号：US12943379
申请日：2010-11-10
申请人： Sandeep Kumar Goel , Saurabh Gupta , Wei-Pin Changchien , Chin-Chou Liu
发明人： Sandeep Kumar Goel , Saurabh Gupta , Wei-Pin Changchien , Chin-Chou Liu
IPC分类号： G01R23/20
CPC分类号： G01R31/318328
摘要： System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.
摘要翻译：公开了用于有效检测小延迟缺陷的系统和方法。该方法首先加载集成电路的布局信息。然后，基于它们的物理信息将集成电路的网络和路径划分成两组。物理信息包括每个路径和网络的长度以及每个路径和网络处的通道数量。定时感知自动测试模式发生器被配置为产生具有对小延迟缺陷敏感的路径和网络的第一组的测试模式。传统的转换延迟故障测试模式发生器被配置为产生第二组的测试模式。

9. 发明授权

US08140923B2 Test circuit and method for testing of infant mortality related defects 失效
标题翻译：用于测试婴儿死亡率相关缺陷的测试电路和方法
公开(公告)号：US08140923B2
公开(公告)日：2012-03-20
申请号：US12421527
申请日：2009-04-09
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna
IPC分类号： G01R31/28 , G01R35/00 , G01R31/00
CPC分类号： G01R31/31922 , G01R31/3016
摘要： The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.
摘要翻译：本公开提供了IC的实施例和测试IC的方法。在一个实施例中，IC包括：（1）具有节点和至少一个顺序逻辑元件的功能逻辑路径和（2）耦合到功能逻辑路径并具有延迟块的测试电路，所述测试电路被配置为形成响应于测试模式信号包括延迟块和节点的可测试路径，其中选择延迟块的延迟值以检测与该节点相关联的小延迟缺陷。

10. 发明授权

US07076709B2 Testing of circuit with plural clock domains 失效
标题翻译：具有多个时钟域的电路测试
公开(公告)号：US07076709B2
公开(公告)日：2006-07-11
申请号：US10502825
申请日：2002-12-23
申请人： Hubertus Gerardus Hendrikus Vermeulen , Sandeep Kumar Goel
发明人： Hubertus Gerardus Hendrikus Vermeulen , Sandeep Kumar Goel
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318558 , G01R31/318583 , G01R31/318594
摘要： An electronic circuit has a plurality of sub-circuits. Clock gate circuits supply gated clock signals to data storage elements of the sub-circuits. The clock gate circuits have gate inputs for receiving gate signals that commands blocking passage of the clock signal. Data can be transferred between data storage elements between two of the subcircuits. A detector circuit flags invalid data in the data storage element of the second one of the sub-circuits. The detector circuit has a flag storage element arranged to set a flag when the clock gate circuit of the second one of the sub-circuits passes the clock signal for the second one of the sub-circuits after the clock gate of the first one of the sub-circuits has blocked the clock signal for the first one of the sub-circuits. The flag indicates the relative phase of the clocks signals of different sub-circuits when the clocks are stopped. The flag is used to invalidate data in the data storage element of the second one of the sub-circuits.
摘要翻译：电子电路具有多个子电路。时钟门电路将门控时钟信号提供给子电路的数据存储元件。时钟门电路具有用于接收控制时钟信号通过的门信号的门输入。数据可以在两个子电路之间的数据存储元件之间传输。检测器电路在第二子电路的数据存储元件中标记无效数据。检测器电路具有标志存储元件，该标志存储元件被布置成当第二个子电路的时钟门电路在第一个子电路的第一个的时钟门经过子电路中的第二个子电路的时钟信号之后，设置标志子电路阻塞了第一个子电路的时钟信号。标志表示时钟停止时不同子电路的时钟信号的相对相位。该标志用于使第二个子电路的数据存储元件中的数据无效。

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