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1. 发明授权

US07171638B2 Methods of screening ASIC defects using independent component analysis of quiescent current measurements 有权
标题翻译：使用静态电流测量的独立分量分析来筛选ASIC缺陷的方法
公开(公告)号：US07171638B2
公开(公告)日：2007-01-30
申请号：US10969745
申请日：2004-10-20
申请人： Ritesh P. Turakhia , Robert B. Benware
发明人： Ritesh P. Turakhia , Robert B. Benware
IPC分类号： G06F17/50
CPC分类号： G01R31/3008
摘要： A method and computer program for screening defects in integrated circuit die includes steps of receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die and generating a test matrix from the quiescent current measurements for each die in the sample lot. A de-mixing matrix is computed from independent component analysis that models passing die in the sample lot. A matrix of sources is generated as a product of the test matrix and the de-mixing matrix. The matrix of sources is normalized to zero mean and unit variance. A statistical limit of the passing die in the sample lot is selected from each of the sources in the normalized matrix of sources to determine a maximum and a minimum quiescent current limit for each of the sources. The maximum and the minimum quiescent current limit for each of the sources is generated as output.
摘要翻译：用于筛选集成电路裸片中的缺陷的方法和计算机程序包括以下步骤：在半导体管芯的样本批中接收每个管芯的静态电流的输入测量值，并从样品批中每个管芯的静态电流测量值生成测试矩阵。从独立分量分析中计算出一个去混合矩阵，对分析样本中的模具进行模拟。产生源矩阵作为测试矩阵和解混合矩阵的乘积。源矩阵被归一化为零均值和单位方差。从源的归一化矩阵中的每个源中选择样本批中的通过芯片的统计限制，以确定每个源的最大和最小静态电流限制。产生每个源的最大和最小静态电流限制作为输出。

2. 发明授权

US08352818B2 Method for generating test patterns for small delay defects 失效
标题翻译：用于生成小延迟缺陷的测试模式的方法
公开(公告)号：US08352818B2
公开(公告)日：2013-01-08
申请号：US12336472
申请日：2008-12-16
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328
摘要： A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
摘要翻译：公开了一种用于产生用于检测IC的小延迟缺陷的测试图案集的方法。在一个实施例中，该方法包括：（1）产生传统的延迟故障模式，（2）对小延迟缺陷覆盖的传统延迟故障模式进行故障分级，（3）报告故障等级检测到的故障和与检测到的故障，（4）确定哪个检测到的故障是采用延迟信息的定时感知目标故障，以及（5）为定时感知目标故障产生定时感知延迟故障模式。

3. 发明申请

US20100153795A1 METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS 失效
标题翻译：用于生成小延迟缺陷的测试模式的方法
公开(公告)号：US20100153795A1
公开(公告)日：2010-06-17
申请号：US12336472
申请日：2008-12-16
申请人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
发明人： Sandeep Kumar Goel , Narendra B. Devta-Prasanna , Ritesh P. Turakhia
IPC分类号： G06F11/16
CPC分类号： G01R31/318328
摘要： A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.
摘要翻译：公开了一种用于产生用于检测IC的小延迟缺陷的测试图案集的方法。在一个实施例中，该方法包括：（1）产生传统的延迟故障模式，（2）对小延迟缺陷覆盖的传统延迟故障模式进行故障分级，（3）报告故障等级检测到的故障和与检测到的故障，（4）确定哪个检测到的故障是采用延迟信息的定时感知目标故障，以及（5）为定时感知目标故障产生定时感知延迟故障模式。

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