专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100297834A1 METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE 有权
标题翻译：在平面表面上使用介质蚀刻停止来减少介电覆盖的方法
公开(公告)号：US20100297834A1
公开(公告)日：2010-11-25
申请号：US12849292
申请日：2010-08-03
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

2. 发明申请

US20110306177A1 METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE 审中-公开
标题翻译：在平面表面上使用介质蚀刻停止来减少介电覆盖的方法
公开(公告)号：US20110306177A1
公开(公告)日：2011-12-15
申请号：US13215836
申请日：2011-08-23
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/82
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A method is described for reducing dielectric overetch. The method includes: (1) forming a substantially planar surface that coexposes conductive or semiconductor features and a dielectric etch stop layer, the conductive or semiconductor features including pillars that each include a vertically oriented diode; (2) depositing second dielectric fill directly on the planar surface; and (3) etching a void in the second dielectric fill, wherein the etch is selective between the second dielectric fill and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer. Numerous other aspects are provided.
摘要翻译：描述了一种减少电介质过蚀刻的方法。该方法包括：（1）形成共同导电或半导体特征和介电蚀刻停止层的基本平坦的表面，所述导电或半导体特征包括每个包括垂直取向的二极管的柱; （2）将第二电介质填充物直接沉积在平面上; 以及（3）蚀刻所述第二介电填充物中的空隙，其中所述蚀刻在所述第二介电填充物和所述电介质蚀刻停止层之间是选择性的，其中所述蚀刻停止在所述电介质蚀刻停止层上。提供了许多其他方面。

3. 发明授权

US07790607B2 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US07790607B2
公开(公告)日：2010-09-07
申请号：US11923687
申请日：2007-10-25
申请人： Samuel V. Dunton , Usha Raghuram , Christopher J. Petti
发明人： Samuel V. Dunton , Usha Raghuram , Christopher J. Petti
IPC分类号： H01L21/4763
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

4. 发明授权

US08008187B2 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US08008187B2
公开(公告)日：2011-08-30
申请号：US12849292
申请日：2010-08-03
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/4763
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

5. 发明申请

US20080254615A1 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US20080254615A1
公开(公告)日：2008-10-16
申请号：US11923687
申请日：2007-10-25
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/306 , H01L21/768
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

6. 发明授权

US08809128B2 Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
标题翻译：用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化
公开(公告)号：US08809128B2
公开(公告)日：2014-08-19
申请号：US12911900
申请日：2010-10-26
申请人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
发明人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
IPC分类号： H01L21/82 , H01L27/24
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。公开了许多附加方面。

7. 发明授权

US08785294B2 Silicon carbide lamina 失效
标题翻译：碳化硅层
公开(公告)号：US08785294B2
公开(公告)日：2014-07-22
申请号：US13558843
申请日：2012-07-26
申请人： Venkatesan Murali , Steve Babayan , Christopher J. Petti
发明人： Venkatesan Murali , Steve Babayan , Christopher J. Petti
IPC分类号： H01L21/30
CPC分类号： H01L33/0079 , H01L21/76254 , H01L29/2003 , H01L29/66462 , H01L29/7786 , H01L33/007
摘要： A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.
摘要翻译：一种制造电子器件的方法包括提供碳化硅或类金刚石碳供体，并将离子注入施主体的第一表面以限定解理面。在注入之后，在第一表面上形成外延层，并且临时载体耦合到外延层。在切割平面处从供体体中切割薄层，并将临时载体从层中移除。在一些实施例中，从层板和外延层制造发光二极管或高电子迁移率晶体管。

8. 发明授权

US08497204B2 Method for reducing dielectric overetch when making contact to conductive features 有权
标题翻译：在与导电特征接触时减小介质过蚀刻的方法
公开(公告)号：US08497204B2
公开(公告)日：2013-07-30
申请号：US13087646
申请日：2011-04-15
申请人： Christopher J. Petti
发明人： Christopher J. Petti
IPC分类号： H01L21/311
CPC分类号： H01L21/768 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种方法，其包括：在第一介电材料上方形成多个导电或半导体特征; 在导电或半导体特征之上沉积第二电介质材料; 蚀刻所述第二电介质材料中的空隙，其中所述蚀刻在所述第一和第二电介质材料之间是选择性的，并且所述蚀刻停止在所述第一电介质材料上; 以及暴露导电或半导体特征的一部分。提供了许多其他方面。

9. 发明授权

US08247260B2 Method to form a photovoltaic cell comprising a thin lamina 有权
标题翻译：形成包括薄层的光伏电池的方法
公开(公告)号：US08247260B2
公开(公告)日：2012-08-21
申请号：US12499294
申请日：2009-07-08
申请人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
发明人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/00 , H01L21/30 , H01L31/042
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.
摘要翻译：通过在诸如半导体晶片的施主体的表面下方注入气体离子形成非常薄的光伏电池。离子注入限定了解理面，随后的步骤在切割平面处从晶片剥离薄层。光伏电池，或光伏电池的基极或发射极的全部或一部分形成在层内。在优选实施例中，在切割步骤之前将晶片固定到接收器。电接触可以形成在层的两个表面上，或仅形成在一个表面上。

10. 发明申请

US20110156044A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式