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1. 发明授权

US07790607B2 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US07790607B2
公开(公告)日：2010-09-07
申请号：US11923687
申请日：2007-10-25
申请人： Samuel V. Dunton , Usha Raghuram , Christopher J. Petti
发明人： Samuel V. Dunton , Usha Raghuram , Christopher J. Petti
IPC分类号： H01L21/4763
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

2. 发明申请

US20110306177A1 METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE 审中-公开
标题翻译：在平面表面上使用介质蚀刻停止来减少介电覆盖的方法
公开(公告)号：US20110306177A1
公开(公告)日：2011-12-15
申请号：US13215836
申请日：2011-08-23
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/82
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A method is described for reducing dielectric overetch. The method includes: (1) forming a substantially planar surface that coexposes conductive or semiconductor features and a dielectric etch stop layer, the conductive or semiconductor features including pillars that each include a vertically oriented diode; (2) depositing second dielectric fill directly on the planar surface; and (3) etching a void in the second dielectric fill, wherein the etch is selective between the second dielectric fill and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer. Numerous other aspects are provided.
摘要翻译：描述了一种减少电介质过蚀刻的方法。该方法包括：（1）形成共同导电或半导体特征和介电蚀刻停止层的基本平坦的表面，所述导电或半导体特征包括每个包括垂直取向的二极管的柱; （2）将第二电介质填充物直接沉积在平面上; 以及（3）蚀刻所述第二介电填充物中的空隙，其中所述蚀刻在所述第二介电填充物和所述电介质蚀刻停止层之间是选择性的，其中所述蚀刻停止在所述电介质蚀刻停止层上。提供了许多其他方面。

3. 发明申请

US20100297834A1 METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE 有权
标题翻译：在平面表面上使用介质蚀刻停止来减少介电覆盖的方法
公开(公告)号：US20100297834A1
公开(公告)日：2010-11-25
申请号：US12849292
申请日：2010-08-03
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

4. 发明授权

US07422985B2 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US07422985B2
公开(公告)日：2008-09-09
申请号：US11090526
申请日：2005-03-25
申请人： Samuel V Dunton , Christopher J Petti , Usha Raghuram
发明人： Samuel V Dunton , Christopher J Petti , Usha Raghuram
IPC分类号： H01L21/302
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。在优选实施例中，导电或半导体特征是形成垂直取向的二极管的柱。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

5. 发明授权

US08008187B2 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US08008187B2
公开(公告)日：2011-08-30
申请号：US12849292
申请日：2010-08-03
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/4763
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

6. 发明申请

US20080254615A1 Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
标题翻译：在平坦表面使用电介质蚀刻停止来减少介电过程的方法
公开(公告)号：US20080254615A1
公开(公告)日：2008-10-16
申请号：US11923687
申请日：2007-10-25
申请人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
发明人： Samuel V. Dunton , Christopher J. Petti , Usha Raghuram
IPC分类号： H01L21/306 , H01L21/768
CPC分类号： H01L27/1021 , H01L21/76802 , H01L21/76829 , Y10S438/90
摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
摘要翻译：基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或半导体功能。

7. 发明申请

US20090273022A1 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH 审中-公开
标题翻译：导电硬掩模，以保护在TRENCH ETCH期间的图案特征
公开(公告)号：US20090273022A1
公开(公告)日：2009-11-05
申请号：US12502796
申请日：2009-07-14
申请人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
发明人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
IPC分类号： H01L27/105 , H01L21/8234 , H01L21/822 , H01L27/06
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described.
摘要翻译：单片三维存储器阵列通过一种方法形成，该方法包括通过在第一方向上形成多个沿第一方向延伸的多个第一基本上平行的导体形成第一存储器电平，ii）在第一导体上方形成第一柱，柱，其包括在垂直取向的二极管上方的第一导电层或层堆叠，在单个光刻步骤中形成的第一柱，iii）在第一柱上方沉积第一电介质层，以及iv）在第一栅极中蚀刻多个基本上平行的第一沟槽所述第一沟槽在第二方向上延伸，其中在所述蚀刻步骤之后，所述沟槽中的最低点高于所述第一导电层或层堆叠的最低点，其中所述第一导电层或所述层堆叠不包含电阻率开关金属氧化物或氮化物。该方法还包括在第一存储器级上方单片地形成第二存储器级。还描述了其他方面。

8. 发明申请

US20070284656A1 Conductive hard mask to protect patterned features during trench etch 失效
标题翻译：导电硬掩模，用于在沟槽蚀刻期间保护图案特征
公开(公告)号：US20070284656A1
公开(公告)日：2007-12-13
申请号：US11444936
申请日：2006-05-31
申请人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
发明人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.
摘要翻译：提供了一种使用导电硬掩模形成图案化特征的方法，其中导电硬掩模在随后的沟槽蚀刻期间保护这些特征以形成提供从上方到那些特征的电连接的大马士革导体。硬掩模的厚度提供了一个余量，以避免在沟槽蚀刻期间的过蚀刻，这可能对器件性能有害。该方法有利地用于形成单片三维存储器阵列。

9. 发明授权

US07307013B2 Nonselective unpatterned etchback to expose buried patterned features 失效
标题翻译：曝光掩埋图案特征的无选择性无图案蚀刻
公开(公告)号：US07307013B2
公开(公告)日：2007-12-11
申请号：US10883417
申请日：2004-06-30
申请人： Usha Raghuram , Michael W. Konevecki , Samuel V. Dunton
发明人： Usha Raghuram , Michael W. Konevecki , Samuel V. Dunton
IPC分类号： H01L21/461 , C03C25/68 , C23F1/00
CPC分类号： H01L21/7684 , H01L21/31055 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/76819 , H01L27/101 , H01L27/1021
摘要： A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the first material. The second material is preferably self-planarizing during deposition. An unpatterned etch is performed to etch the second material and expose the top of the buried features of the first material. The etch is preferably a two-stage etch: The first stage is selective to the second material. When the second material is exposed, the etch chemistry is changed such that the etch is nonselective, etching the first material and the second material at substantially the same rate until the buried features are exposed across the wafer, producing a substantially planar surface.
摘要翻译：公开了一种用于蚀刻以形成平坦化表面的方法。隔开的特征由第一材料形成，第一材料是导电的或绝缘的。第二材料沉积在第一材料之上和之间。第二种材料是绝缘的或导电的，与第一种材料的电导率相反。第二种材料优选在沉积期间是自平面化的。执行未图案化的蚀刻以蚀刻第二材料并暴露第一材料的掩埋特征的顶部。蚀刻优选是两阶段蚀刻：第一阶段对第二材料是选择性的。当暴露第二材料时，蚀刻化学物质被改变，使得蚀刻是非选择性的，以基本上相同的速率蚀刻第一材料和第二材料，直到掩埋特征暴露在晶片之外，产生基本平坦的表面。

10. 发明授权

US07575984B2 Conductive hard mask to protect patterned features during trench etch 失效
标题翻译：导电硬掩模，用于在沟槽蚀刻期间保护图案特征
公开(公告)号：US07575984B2
公开(公告)日：2009-08-18
申请号：US11444936
申请日：2006-05-31
申请人： Steven J Radigan , Usha Raghuram , Samuel V Dunton , Michael W Konevecki
发明人： Steven J Radigan , Usha Raghuram , Samuel V Dunton , Michael W Konevecki
IPC分类号： H01L21/326 , H01L21/82 , H01L21/44
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.
摘要翻译：提供了一种使用导电硬掩模形成图案化特征的方法，其中导电硬掩模在随后的沟槽蚀刻期间保护这些特征以形成提供从上方到那些特征的电连接的大马士革导体。硬掩模的厚度提供了一个余量，以避免在沟槽蚀刻期间的过蚀刻，这可能对器件性能有害。该方法有利地用于形成单片三维存储器阵列。

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