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1. 发明授权

US08880382B2 Analyzing a patterning process using a model of yield 有权
公开(公告)号：US08880382B2
公开(公告)日：2014-11-04
申请号：US13352713
申请日：2012-01-18
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
IPC分类号： G06G7/48
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

2. 发明授权

US08682634B2 Analyzing a patterning process using a model of yield 失效
标题翻译：使用产量模型分析图案化过程
公开(公告)号：US08682634B2
公开(公告)日：2014-03-25
申请号：US13613061
申请日：2012-09-13
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
摘要翻译：提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。使用电路产量结果，确定至少模拟装置形状的高级特征。基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到满足至少一个第一预定标准。构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

3. 发明申请

US20130185046A1 Analyzing A Patterning Process Using A Model Of Yield 失效
标题翻译：使用产量模型分析模式化过程
公开(公告)号：US20130185046A1
公开(公告)日：2013-07-18
申请号：US13613061
申请日：2012-09-13
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E. Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E. Rosenbluth , Rama N. Singh , Kehan Tian
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
摘要翻译：提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。使用电路产量结果，确定至少模拟装置形状的高级特征。基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到满足至少一个第一预定标准。构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

4. 发明申请

US20110173577A1 Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields 审中-公开
标题翻译：用于最大化过程敏感电路产量的模式过程调优和设计优化技术
公开(公告)号：US20110173577A1
公开(公告)日：2011-07-14
申请号：US12024390
申请日：2008-02-01
申请人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
发明人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.
摘要翻译：提供了改进电路设计和生产的技术。一方面，提供了一种用于虚拟制造过程敏感电路的方法。该方法包括以下步骤。基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。基于质量的度量用于为制造的电路的虚拟表示投影产量。物理布局图和/或生产过程被修改。重复获得，使用和修改步骤，直到达到期望的预计产量。

5. 发明申请

US20100269079A1 Analyzing Multiple Induced Systematic and Statistical Layout Dependent Effects On Circuit Performance 有权
标题翻译：分析多个诱导系统和统计布局对电路性能的依赖性影响
公开(公告)号：US20100269079A1
公开(公告)日：2010-10-21
申请号：US12426475
申请日：2009-04-20
申请人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
发明人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.
摘要翻译：一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

6. 发明授权

US07673195B2 Circuits and methods for characterizing device variation in electronic memory circuits 有权
标题翻译：用于表征电子存储器电路中的器件变化的电路和方法
公开(公告)号：US07673195B2
公开(公告)日：2010-03-02
申请号：US11866502
申请日：2007-10-03
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G11C29/00 , G11C7/06
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变电压差＆Dgr ;在它们的栅 - 源电压之间，和（ii）改变＆Dgr; 直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

7. 发明申请

US20090310430A1 METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS 有权
标题翻译：用于表征电子存储器电路中器件变化的方法
公开(公告)号：US20090310430A1
公开(公告)日：2009-12-17
申请号：US12542187
申请日：2009-08-17
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G11C29/00 , G01R19/00 , G11C11/00 , G01R31/08
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变的电压差在其栅极至源极电压之间，和（ii）改变增量，直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

8. 发明申请

US20070171748A1 Sense amplifier circuit 失效
公开(公告)号：US20070171748A1
公开(公告)日：2007-07-26
申请号：US11337348
申请日：2006-01-23
申请人： Saibal Mukhopadhyay , Hamid Mahmoodi , Kaushik Roy
发明人： Saibal Mukhopadhyay , Hamid Mahmoodi , Kaushik Roy
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C11/413
摘要： A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

9. 发明授权

US08418087B2 Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance 失效
标题翻译：分析多个诱导的系统和统计布局对电路性能的影响
公开(公告)号：US08418087B2
公开(公告)日：2013-04-09
申请号：US13371537
申请日：2012-02-13
申请人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
发明人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.
摘要翻译：一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

10. 发明授权

US07508697B1 Self-repairing technique in nano-scale SRAM to reduce parametric failures 失效
标题翻译：纳米级SRAM中的自修复技术可减少参数故障
公开(公告)号：US07508697B1
公开(公告)日：2009-03-24
申请号：US11746448
申请日：2007-05-09
申请人： Saibal Mukhopadhyay , Hamid Mahmoodi , Keejong Kim , Kaushik Roy
发明人： Saibal Mukhopadhyay , Hamid Mahmoodi , Keejong Kim , Kaushik Roy
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/028 , G11C29/4401 , G11C2029/5006
摘要： A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process corners, in response to which the SRAM applies adaptive body bias to reduce the number of parametric failures in a die and improve memory yield. Embodiments include circuitry for applying reverse body bias (RBB) to the SRAM array in the presence of a low inter-die Vt process corner, thereby reducing possible read and hold failures, and applying forward body bias (FBB) to the array in the presence of a high inter-die Vt process corner, thereby reducing possible access and write failures.
摘要翻译：一种自修复SRAM和一种减少SRAM中参数故障的方法。采用片内泄漏或延迟监测器来检测晶片间Vt过程角，响应于此，SRAM应用自适应体偏置以减少管芯中参数故障的数量并提高记忆产量。实施例包括用于在存在低的晶片间Vt处理角的情况下将反向偏置（RBB）施加到SRAM阵列的电路，从而减少可能的读取和保持故障，并且在存在时向阵列应用前向偏置（FBB）的高间隔Vt处理角，从而减少可能的访问和写入失败。

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