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1. 发明申请

WO2013158556A1 SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS 审中-公开
标题翻译：具有选择性抑制通过位置的3D非易失性存储器的软擦除操作
公开(公告)号：WO2013158556A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036615
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/16 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障比特。

2. 发明申请

WO2013180893A1 THRESHOLD VOLTAGE ADJUSTMENT FOR A SELECT GATE TRANSISTOR IN A STACKED NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：堆叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
公开(公告)号：WO2013180893A1
公开(公告)日：2013-12-05
申请号：PCT/US2013/039505
申请日：2013-05-03
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C29/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

3. 发明申请

WO2013158557A1 ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT 审中-公开
标题翻译：具有可控门控感应漏水电流的3D非易失性存储器的擦除操作
公开(公告)号：WO2013158557A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036616
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/06 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate- induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以受益于更高的栅极引起的漏极泄漏（GIDL）电流以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

4. 发明申请

WO2014066263A1 DYNAMIC BIT LINE BIAS FOR PROGRAMMING NON-VOLATILE MEMORY 审中-公开
标题翻译：用于编程非易失性存储器的动态位线偏移
公开(公告)号：WO2014066263A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/065969
申请日：2013-10-21
申请人： SANDISK TECHNOLOGIES,INC. , DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C11/56 , G11C16/12 , G11C7/12 , G11C16/24
CPC分类号： G11C16/10 , G11C7/12 , G11C11/5628 , G11C16/12 , G11C16/24 , G11C16/3459
摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
摘要翻译：用于一组非易失性存储元件的程序操作。维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。可以使用不同的位线电压，具有公共的步长或不同的步长。结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。在缓慢编程模式下，锁存器保持相关存储元件所经历的编程脉冲计数。当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。

5. 发明申请

WO2014071175A1 INTEGRATION OF SINGLE-LEVEL AND MULTI-LEVEL FLASH CELLS HAVING DIFFERENT TUNNEL OXIDE THICKNESSES 审中-公开
标题翻译：具有不同隧道氧化物厚度的单层和多层闪电池的整合
公开(公告)号：WO2014071175A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/068036
申请日：2013-11-01
申请人： SANDISK TECHNOLOGIES, INC. , HIGASHITANI, Masaaki , DUNGA, Mohan , YUAN, Jiahui
发明人： HIGASHITANI, Masaaki , DUNGA, Mohan , YUAN, Jiahui
IPC分类号： H01L21/28 , G11C11/56 , H01L27/115
CPC分类号： G11C11/5628 , G11C2211/5641 , H01L21/28273 , H01L27/11521 , H01L27/11524
摘要： Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide (712b) may be used for memory cells in SLC blocks (202b) than for memory cells in MLC blocks (202a). A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide (712a) in MLC blocks may improve data retention. A thinner IPD (708b) may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD (708a) in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks.
摘要翻译：公开了具有与MLC块不同特性的SLC块的技术，使得SLC块将具有高耐久性，并且MLC块将具有高可靠性。较薄的隧道氧化物（712b）可用于SLC块（202b）中的存储器单元而不是MLC块（202a）中的存储单元。 SLC块中较薄的隧道氧化物可能允许使用较低的编程电压，这可以提高耐久性。 MLC块中较厚的隧道氧化物（712a）可以改善数据保留。可以将较薄的IPD（708b）用于SLC块中的存储单元，而不是MLC块中的存储单元。更薄的IPD可以提供更高的耦合比，这可以允许较低的编程电压。 SLC块中较低的编程电压可以提高耐久性。 MLC块中较厚的IPD（708a）可以防止或减少读取干扰。 SLC块可以具有与MLC块不同数量的数据字线。

6. 发明申请

WO2014088803A1 NON-VOLATILE STORAGE NAND STRING SELECT GATE VOLTAGE LOWERED DURING PROGRAMMING 审中-公开
标题翻译：非易失性存储NAND STRING在编程期间选择门电压降低
公开(公告)号：WO2014088803A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/070841
申请日：2013-11-19
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
发明人： DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
IPC分类号： G11C16/24 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/24
摘要： Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.
摘要翻译：本文公开的技术可以通过防止未选择的NAND串的选择晶体管无意地导通来阻止程序干扰。 NAND串的选择晶体管的Vgs可以从一个编程脉冲多次降低到下一个编程脉冲。选择晶体管可以是漏极侧选择晶体管或源极侧选择晶体管。随着编程进行，逐渐降低未选择的NAND串的选择晶体管的Vgs可以防止选择晶体管无意地导通。因此，防止或减少程序干扰。可以通过对与选择晶体管相关联的选择线施加较低的电压来降低Vgs。当编程进行时，可以通过对与未选择的NAND串相关联的位线施加更高的电压来降低Vgs。当编程进行时，Vgs可以通过对公共源极线施加更高的电压来降低。

7. 发明申请

WO2013176858A1 CONTROLLING DUMMY WORD LINE BIAS DURING ERASE IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中控制消除字线偏差
公开(公告)号：WO2013176858A1
公开(公告)日：2013-11-28
申请号：PCT/US2013/039209
申请日：2013-05-02
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , DUNGA, Mohan , HIGASHITANI, Masaaki
发明人： DUTTA, Deepanshu , DUNGA, Mohan , HIGASHITANI, Masaaki
IPC分类号： G11C16/16 , G11C11/56 , G11C7/10
CPC分类号： G11C16/14 , G11C7/1006 , G11C11/5635 , G11C16/0483 , G11C16/16
摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.
摘要翻译：一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。选择栅极晶体管的电压也可以电容耦合得更高。衬底电压可以逐步增加和/或作为连续斜坡增加。在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。在另一种方法中，外部和内部虚拟存储元件都浮起来。由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。

8. 发明申请

WO2013155329A1 FABRICATING 3D NON-VOLATILE STORAGE WITH ADDITIONAL WORD LINE SELECT GATES 审中-公开
标题翻译：使用附加字线选择门框制作3D非易失性存储
公开(公告)号：WO2013155329A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/036213
申请日：2013-04-11
申请人： SANDISK TECHNOLOGIES, INC. , RABKIN, Peter , HIGASHITANI, Masaaki
发明人： RABKIN, Peter , HIGASHITANI, Masaaki
IPC分类号： H01L29/66 , H01L29/786 , H01L27/115 , H01L21/265 , G11C16/08
CPC分类号： H01L29/66757 , G11C16/0483 , G11C16/06 , G11C16/08 , H01L21/02532 , H01L21/02595 , H01L21/04 , H01L21/26513 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/66477 , H01L29/66742 , H01L29/6675 , H01L29/66787 , H01L29/785 , H01L29/78642 , H01L29/78696 , H01L29/7926
摘要： Disclosed herein are techniques for fabricating a 3D stacked memory device having word line (WL) select gates (229). The bodies (231) of the WL select gates may be formed from the same material (e.g., highly doped polysilicon) that the word lines are formed of. Desired doping profiles in a body of a WL select gate may be achieved by various techniques such as counter-doping. The WL select gates may include TFTs that are formed by etching holes in the layer in which word lines are formed. Gate electrodes (404) and gate dielectrics (402) may be formed in the holes. Bodies may be formed in the polysilicon outside of the holes.
摘要翻译：这里公开了用于制造具有字线（WL）选择门（229）的3D堆叠存储器件的技术。 WL选择栅极的主体（231）可以由字线形成的相同材料（例如，高掺杂多晶硅）形成。可以通过各种技术（例如反掺杂）来实现在WL选择栅极的体内期望的掺杂分布。 WL选择栅极可以包括通过在其中形成字线的层中蚀刻孔而形成的TFT。可以在孔中形成栅极（404）和栅极电介质（402）。体可以形成在孔外的多晶硅中。

9. 发明申请

WO2013155325A1 3D NON-VOLATILE STORAGE WITH ADDITIONAL WORD LINE SELECT GATES 审中-公开
标题翻译： 3D非挥发性存储与附加字线选择门
公开(公告)号：WO2013155325A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/036208
申请日：2013-04-11
申请人： SANDISK TECHNOLOGIES, INC. , RABKIN, Peter , HIGASHITANI, Masaaki
发明人： RABKIN, Peter , HIGASHITANI, Masaaki
IPC分类号： H01L29/66 , H01L29/786 , H01L27/115 , H01L21/265 , G11C16/08
CPC分类号： H01L29/66757 , G11C16/0483 , G11C16/06 , G11C16/08 , H01L21/02532 , H01L21/02595 , H01L21/04 , H01L21/26513 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/66477 , H01L29/66742 , H01L29/6675 , H01L29/66787 , H01L29/785 , H01L29/78642 , H01L29/78696 , H01L29/7926
摘要： Disclosed herein are 3D stacked memory devices having WL select gates (229). The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area (301) of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors (231, 402, 404). 3D decoding may be provided in a 3D stacked memory device using the WL select gates.
摘要翻译：这里公开了具有WL选择门的3D堆叠存储器件（229）。 3D堆叠存储器件可以具有NAND串。 WL选择栅极可以位于与字线板的字线连接区域（301）相邻的位置。字线板可以由字线驱动器驱动，并且可以具有许多字线。 WL选择门可以选择单个字线或字线组。因此，可以选择整个块的较小单元。这可能会降低电容负载。 WL选择栅极可以包括薄膜晶体管（231,402,404）。可以使用WL选择门在3D堆叠存储器件中提供3D解码。

10. 发明申请

WO2011149823A1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHRONIZED COUPLING 审中-公开
标题翻译：编程具有同步耦合的非易失性存储
公开(公告)号：WO2011149823A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/037526
申请日：2011-05-23
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected tol5 a group of connected non-volatile storage elements. The set of word lines includes a selected word line(WLn), unselected word lines (WLn+1/WLn- 1) that are adjacent to the selected word line and other unselected word lines (WLunse1). After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage (Vpgm) and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels (Vint1, Vint2, Vint3 ) concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
摘要翻译：用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。编程过程包括提高连接到一组连接的非易失性存储元件的一组字线的电压。该字线组包括与所选择的字线和其他未被选择的字线（WLunse1）相邻的所选字线（WLn），未选字线（WLn + 1 / WLn-1）。在对所述一组字线提升电压之后，所述处理包括将所选择的字线升高到编程电压（Vpgm），并将与所选字线相邻的未选字线提升到一个或多个电压电平（Vint1，Vint2， Vint3）同时将选定的字线提升到编程电压。程序电压使至少一个非易失性存储元件经历编程。

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