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1. 发明申请

WO2013158556A1 SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS 审中-公开
标题翻译：具有选择性抑制通过位置的3D非易失性存储器的软擦除操作
公开(公告)号：WO2013158556A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036615
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/16 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障比特。

2. 发明申请

WO2013180893A1 THRESHOLD VOLTAGE ADJUSTMENT FOR A SELECT GATE TRANSISTOR IN A STACKED NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：堆叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
公开(公告)号：WO2013180893A1
公开(公告)日：2013-12-05
申请号：PCT/US2013/039505
申请日：2013-05-03
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C29/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

3. 发明申请

WO2013158557A1 ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT 审中-公开
标题翻译：具有可控门控感应漏水电流的3D非易失性存储器的擦除操作
公开(公告)号：WO2013158557A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036616
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/06 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate- induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以受益于更高的栅极引起的漏极泄漏（GIDL）电流以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

4. 发明申请

WO2013095832A1 ERASE INHIBIT FOR 3D NON-VOLATILE MEMORY 审中-公开
标题翻译：消除三维非易失性存储器的禁止
公开(公告)号：WO2013095832A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/065740
申请日：2012-11-19
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying
发明人： LI, Haibo , COSTA, Xiying
IPC分类号： G11C16/16 , G11C16/04 , G11C16/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/344
摘要： An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test (518), then a one-sided erase of the remaining NAND strings is performed (526). The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends (510), while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition (518), such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test (516, 520). As a result, erase degradation of the memory cells is reduced.
摘要翻译：用于3D堆叠存储器件的擦除处理执行NAND串的双面擦除，直到多个NAND串中的一个通过擦除验证测试（518），然后执行剩余NAND串的单面擦除（ 526）。双面擦除从源极侧和漏极端（510）向NAND串的主体充电，而单面擦除从漏极侧端部充电NAND串的本体。与一个位线相关联的NAND串形成一组。当设置满足设置的擦除验证条件（518）时，可能会切换到单面擦除，例如通过擦除验证测试的组的NAND串的一个，全部或某些指定部分。当不超过指定数量的NAND串未达到擦除验证测试（516,520）时，擦除操作可以结束。结果，存储单元的擦除劣化降低。

5. 发明申请

WO2013095831A1 ERASE OPERATION WITH CONTROLLED SELECT GATE VOLTAGE FOR 3D NON-VOLATILE MEMORY 审中-公开
标题翻译：用于3D非易失性存储器的控制选择栅极电压的擦除操作
公开(公告)号：WO2013095831A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/065739
申请日：2012-11-19
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying , ZHANG, Chenfeng
发明人： LI, Haibo , COSTA, Xiying , ZHANG, Chenfeng
IPC分类号： G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line (504, 506, 508). A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage (506) to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration (512) of an erase operation, or at a predetermined or adaptively determined erase-verify iteration (516), such as based on a number of program-erase cycles.
摘要翻译：用于3D堆叠存储器件的擦除处理控制NAND串的漏极侧选择栅极（SGD）和源极选择栅极（SGS）。在一种方法中，驱动SGD和SGS以在选择栅极上提供可预测的漏极到栅极电压，同时将擦除电压施加到位线或源极线（504,506,508）。可以产生在选择栅极处更一致的栅极引起的漏极漏极（GIDL），以对NAND串的体进行充电。此外，可以利用擦除电压（506）来升高选择栅极电压，以避免导致退化的选择栅极两端的漏极 - 栅极电压过大。选择栅极电压的升高可以从擦除操作的第一擦除验证迭代（512）开始，或者以预定或自适应确定的擦除验证迭代（516）开始，诸如基于编程擦除的次数周期。

6. 发明申请

WO2014074408A2 3D STACKED NON-VOLATILE STORAGE PROGRAMMING TO CONDUCTIVE STATE 审中-公开
标题翻译： 3D堆叠非易失性存储编程到导电状态
公开(公告)号：WO2014074408A2
公开(公告)日：2014-05-15
申请号：PCT/US2013/068041
申请日：2013-11-01
申请人： SANDISK TECHNOLOGIES, INC. , MIHNEA, Andrei , COSTA, Xiying , ZHANG, Yanli
发明人： MIHNEA, Andrei , COSTA, Xiying , ZHANG, Yanli
IPC分类号： G11C11/56 , G11C16/10 , H01L27/115
CPC分类号： G11C11/5671 , G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11582
摘要： Programming NAND strings in a 3D stacked storage device to a conductive state is disclosed. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.
摘要翻译：公开了将3D堆叠存储设备中的NAND串编程为导通状态。存储元件可以通过升高Vt并通过降低Vt进行编程而被擦除。编程可能包括对选定的位线施加一系列增加的电压，直到选定的存储单元被编程为止。未选择的位线可以保持在大约地面或靠近地面。所选择的字线可以接地，或者靠近地面。所选择的字线和位线之间的未被选择的字线可以接收所选位线电压。源极线和所选字线之间的未选字线可以接收大约一半的选定位线电压。可以在不增加未选择的NAND串的通道以阻止它们编程的情况下实现编程。因此，可以避免与提升的通道电位的泄漏相关的程序干扰。

7. 发明申请

WO2011159581A2 MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的存储单元
公开(公告)号：WO2011159581A2
公开(公告)日：2011-12-22
申请号：PCT/US2011/040103
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL, Franz , COSTA, Xiying , KAI, James , MAKALA, Raghuveer, S.
发明人： KREUPL, Franz , COSTA, Xiying , KAI, James , MAKALA, Raghuveer, S.
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

8. 发明申请

WO2012044473A1 COUNTER DOPING COMPENSATION METHODS TO IMPROVE DIODE PERFORMANCE 审中-公开
标题翻译：计数器补偿方法提高二极管性能
公开(公告)号：WO2012044473A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/051988
申请日：2011-09-16
申请人： SANDISK 3D, LLC , COSTA, Xiying , BANDYOPADHYAY, Abhijit , HOU, Kun , LE, Brian , CHEN, Yung-Tin
发明人： COSTA, Xiying , BANDYOPADHYAY, Abhijit , HOU, Kun , LE, Brian , CHEN, Yung-Tin
IPC分类号： H01L27/102 , H01L27/24 , H01L45/00
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1675
摘要： A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.
摘要翻译：提供一种形成存储单元的方法，所述方法包括形成二极管，该二极管包括具有第一导电类型的第一区域，对二极管进行反掺杂以将第一区域改变为第二导电类型，以及形成串联耦合的存储元件与二极管。还提供其他方面。

9. 发明申请

WO2012129083A1 CONDITIONAL PROGRAMMING OF MULTIBIT MEMORY CELLS 审中-公开
标题翻译：多位记忆细胞的条件编程
公开(公告)号：WO2012129083A1
公开(公告)日：2012-09-27
申请号：PCT/US2012/029416
申请日：2012-03-16
申请人： SANDISK 3D LLC , COSTA, Xiying , NIAN, Yibo , SCHEUERLEIN, Roy , LIU, Tz-Yi , GORLA, Chandrasekhar, Reddy
发明人： COSTA, Xiying , NIAN, Yibo , SCHEUERLEIN, Roy , LIU, Tz-Yi , GORLA, Chandrasekhar, Reddy
IPC分类号： G11C11/56 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2013/0076 , G11C2013/0092 , G11C2213/32
摘要： Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.
摘要翻译：改进的多级金属氧化物存储单元的编程方法平衡施加的电压和电流，以提供更好的性能。通过为编程中要实现的目标电阻状态确定适当的编程电压和电流限制，然后施加具有确定的设定电气特性的脉冲来实现将存储器单元转换到较低电阻状态的设置编程。将存储器单元转换到较高电阻状态的复位编程通过确定编程中要实现的状态的适当编程电压和可选的电流限制，然后施加具有确定的电特性的脉冲来实现。用于确定适当的设置或复位编程电压和电流值的算法提供有效的编程，而不会对存储元件造成影响。编程脉冲的电气特性可以存储在表查找算法中使用的数据表中。

10. 发明申请

WO2011049830A1 A MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：包含与转向元件兼容的基于碳的可逆电阻开关元件的存储器及其形成方法
公开(公告)号：WO2011049830A1
公开(公告)日：2011-04-28
申请号：PCT/US2010/052859
申请日：2010-10-15
申请人： SANDISK 3D, LLC , XU, Huiwen , PING, Er-Xuan , COSTA, Xiying , KWON, Thomas J.
发明人： XU, Huiwen , PING, Er-Xuan , COSTA, Xiying , KWON, Thomas J.
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L45/1273 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/1616 , H01L45/1691
摘要： Memory cells, and methods of forming such memory cells, are provided that include a steering element (14) coupled to a carbon-based reversible resistivity switching material (12) that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon -based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first cross - sectional area, coupled to a reversible resistivity switching material, such as aC, having a region that has a second cross - sectional area smaller than the first cross - sectional area.
摘要翻译：提供了存储单元和形成这种存储单元的方法，其包括耦合到具有增加的电阻率的碳基可逆电阻率开关材料（12）的转向元件（14）和小于最大值的开关电流用于控制通过碳基可逆电阻率切换材料的电流的导向元件的当前能力。在具体实施例中，根据本发明的方法和装置形成具有第一横截面面积的转向元件，例如二极管，该第二横截面积与可逆电阻率开关材料（例如aC）耦合，具有具有第二十字的区域 - 截面积小于第一横截面积。

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