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1. 发明申请

WO2011149823A1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHRONIZED COUPLING 审中-公开
标题翻译：编程具有同步耦合的非易失性存储
公开(公告)号：WO2011149823A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/037526
申请日：2011-05-23
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected tol5 a group of connected non-volatile storage elements. The set of word lines includes a selected word line(WLn), unselected word lines (WLn+1/WLn- 1) that are adjacent to the selected word line and other unselected word lines (WLunse1). After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage (Vpgm) and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels (Vint1, Vint2, Vint3 ) concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
摘要翻译：用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。编程过程包括提高连接到一组连接的非易失性存储元件的一组字线的电压。该字线组包括与所选择的字线和其他未被选择的字线（WLunse1）相邻的所选字线（WLn），未选字线（WLn + 1 / WLn-1）。在对所述一组字线提升电压之后，所述处理包括将所选择的字线升高到编程电压（Vpgm），并将与所选字线相邻的未选字线提升到一个或多个电压电平（Vint1，Vint2， Vint3）同时将选定的字线提升到编程电压。程序电压使至少一个非易失性存储元件经历编程。

2. 发明申请

WO2008121553A1 NON-VOLATILE STORAGE WITH DECODING OF DATA USING RELIABILITY METRICS BASED ON MULTIPLE READS 审中-公开
标题翻译：基于多项阅读的可靠性度量数据解码的非易失性存储
公开(公告)号：WO2008121553A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/057380
申请日：2008-03-18
申请人： SANDISK CORPORATION , MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
发明人： MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
IPC分类号： G11C16/34 , G11C16/26 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3454 , G11C29/00
摘要： In a non-volatile storage system, data is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.
摘要翻译：在非易失性存储系统中，使用迭代概率解码和多次读取操作对数据进行解码以实现更高的可靠性。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的读取数据。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果没有发生收敛，例如在设定的时间周期内，再次感测到非易失性存储元件的状态，则调整解码器中的可靠性度量的当前值，并且解码再次尝试收敛。在另一种方法中，初始可靠性度量是基于多次读取。可以在解码发生之前准备存储基于感测状态的可靠性度量和调整的表。

3. 发明申请

WO2008121577A1 SOFT BIT DATA TRANSMISSION FOR ERROR CORRECTION CONTROL IN NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器中的错误校正控制的软位数据传输
公开(公告)号：WO2008121577A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/057722
申请日：2008-03-20
申请人： SANDISK CORPORATION , MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
发明人： MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
IPC分类号： G11C11/56 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1068 , G11C7/1006 , G11C16/0483 , G11C16/26 , G11C29/00 , G11C2211/5634
摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.
摘要翻译：使用迭代概率解码对存储在非易失性存储器中的数据进行解码。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果解码失败，则从存储器读取软数据位。在接收到硬读取结果之后以及在软位操作的每个阶段提供初始可靠性度量值。在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。在比较电平的第二子集读取时，可以基于第一子集数据执行解码。

4. 发明申请

WO2012162316A1 RAMPING PASS VOLTAGE TO ENHANCE CHANNEL BOOST IN MEMORY DEVICE, WITH TEMPERATURE COMPENSATION 审中-公开
标题翻译：延长通道电压以增强存储器件中的通道升压，具有温度补偿
公开(公告)号：WO2012162316A1
公开(公告)日：2012-11-29
申请号：PCT/US2012/038992
申请日：2012-05-22
申请人： SANDISK TECHNOLOGIES, INC. , HEMINK, Gerrit, Jan , LEE, Shin-chung , KHANDELWAL, Anubhav , CHIN, Henry , LIANG, Guirong , LEE, Dana
发明人： HEMINK, Gerrit, Jan , LEE, Shin-chung , KHANDELWAL, Anubhav , CHIN, Henry , LIANG, Guirong , LEE, Dana
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。增加可以是渐进的，以斜坡的形式，或逐步的。可以维持第一通道区域的升压水平。施加到一个或多个未选择字线的电压的增加也随着温度而变化。在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

5. 发明申请

WO2012044711A1 MULTI-STEP CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY 审中-公开
标题翻译：多通道通道升压以减少存储器中的通道至浮动闸门耦合
公开(公告)号：WO2012044711A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/053768
申请日：2011-09-28
申请人： SANDISK TECHNOLOGIES, INC. , LUTZE, Jeffrey, W. , CHIN, Henry
发明人： LUTZE, Jeffrey, W. , CHIN, Henry
IPC分类号： G11C16/34 , G11C11/56 , G11C7/02 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3418 , G11C7/02 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.
摘要翻译：在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。在随后的程序验证迭代中，锁定的存储元件进行全通道升压。或者，在锁定之后，可以通过多次程序验证迭代来加强升压。可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

6. 发明申请

WO2011017378A1 PROGRAMMING MEMORY WITH REDUCED PASS VOLTAGE DISTURB AND FLOATING GATE TO-CONTROL GATE LEAKAGE 审中-公开
标题翻译：具有降低输入电压干扰和浮动门控制门控泄漏的编程存储器
公开(公告)号：WO2011017378A1
公开(公告)日：2011-02-10
申请号：PCT/US2010/044317
申请日：2010-08-03
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , CHIN, Henry
发明人： DUTTA, Deepanshu , CHIN, Henry
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn-I neighbor storage element, and applying an optimal pass voltage to WLn-I for each group. Initially, the states of the storage elements on WLn-I are read. A program iteration includes multiple program pulses. A first program pulse (1402) is applied to WLn while a first pass voltage (1425) is applied to WLn-1, a first group (1480, 1482, 1488) of WLn storage elements is selected for programming, and a second group (1484, 1486) of WLn storage elements is inhibited. Next, a second program pulse (1404) is applied to WLn while a second pass voltage (1426) is applied to WLn-I, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states (A, B, C, E).
摘要翻译：通过根据其WLn-I相邻存储元件的状态在分离的组中对所选择的字线WLn上的存储元件进行编程，并且对每个所述WLn-I相邻存储元件的WLn-1施加最佳通过电压，从而在非易失性存储系统中减少编程干扰组。最初，读取WLn-I上的存储元件的状态。程序迭代包括多个程序脉冲。当对WLn-1施加第一通过电压（1425）时，第一编程脉冲（1402）被施加到WLn，WLn存储元件的第一组（1480,1482,1488）被选择用于编程，而第二组（ 1484,1486）的WLn存储元件被禁止。接下来，向WLn施加第二编程脉冲（1404），同时将第二通过电压（1426）施加到WLn-I，选择第二组WLn存储元件进行编程，并且第一组WLn存储元件为抑制。组可以包括一个或多个数据状态（A，B，C，E）。

7. 发明申请

WO2010005878A1 DIELECTRIC CAP ABOVE FLOATING GATE 审中-公开
标题翻译：电磁盖上浮门
公开(公告)号：WO2010005878A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/049620
申请日：2009-07-02
申请人： SANDISK CORPORATION , LEE, Dana , CHIN, Henry , KAI, James , ORIMOTO, Takashi, Whitney , PURAYATH, Vinod, R. , MATAMIS, George
发明人： LEE, Dana , CHIN, Henry , KAI, James , ORIMOTO, Takashi, Whitney , PURAYATH, Vinod, R. , MATAMIS, George
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/265
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324
摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.
摘要翻译：公开了一种包括一组非易失性存储元件的存储器系统。给定的存储单元在浮动栅极上方具有电介质盖。在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。电介质盖减少了浮动栅极和控制栅极之间的漏电流。电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

8. 发明公开

EP2715733A1 RAMPING PASS VOLTAGE TO ENHANCE CHANNEL BOOST IN MEMORY DEVICE, WITH TEMPERATURE COMPENSATION 有权转让
标题翻译： PASSAGE功率的增加，以提高在存储设备中的信道增益带温度补偿
公开(公告)号：EP2715733A1
公开(公告)日：2014-04-09
申请号：EP12725972.9
申请日：2012-05-22
申请人： SanDisk Technologies Inc.
发明人： HEMINK, Gerrit, Jan , LEE, Shin-chung , KHANDELWAL, Anubhav , CHIN, Henry , LIANG, Guirong , LEE, Dana
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.

9. 发明申请

WO2011133412A1 P-TYPE CONTROL GATE IN NON-VOLATILE STORAGE AND METHODS FOR FORMING SAME 审中-公开
标题翻译：非挥发性储存中的P型控制闸门及其形成方法
公开(公告)号：WO2011133412A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032635
申请日：2011-04-15
申请人： SANDISK CORPORATION , ORIMOTO, Takashi Whitney , SUYAMA, Atsushi , TIAN, Ming , CHIN, Henry , CHIEN, Henry , PURAYATH, Vinod Robert , LEE, Dana
发明人： ORIMOTO, Takashi Whitney , SUYAMA, Atsushi , TIAN, Ming , CHIN, Henry , CHIEN, Henry , PURAYATH, Vinod Robert , LEE, Dana
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/28 , H01L29/423
CPC分类号： H01L21/28291 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/788
摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.
摘要翻译：公开了非电压存储和用于制造非易失性存储器的技术。在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。在一个实施例中，控制栅极的下部是p型多晶硅。控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。因此，如果控制门耗尽，可能会发生的一些问题得到缓解。例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

10. 发明申请

WO2010017013A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：WO2010017013A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/050974
申请日：2009-07-17
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻存储元件。

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