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1. 发明申请

WO2013147936A1 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMNMING 审中-公开
标题翻译：在编程期间选定的字线相关选择门限扩展区域电压
公开(公告)号：WO2013147936A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/066610
申请日：2012-11-27
申请人： SANDISK TECHNOLOGIES, INC. , LAI, Chun-Hung , SATO, Shinji , LEE, Shih-Chung , HEMINK, Gerrit Jan
发明人： LAI, Chun-Hung , SATO, Shinji , LEE, Shih-Chung , HEMINK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

2. 发明申请

WO2012087815A1 NON-VOLATILE MEMORY AND METHODS WITH SOFT-BIT READS WHILE READING HARD BITS WITH COMPENSATION FOR COUPLING 审中-公开
标题翻译：非易失性存储器和采用软读取读取硬件位置并进行补偿的方法
公开(公告)号：WO2012087815A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/065461
申请日：2011-12-16
申请人： SANDISK IL LTD. , ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , MOKHLESI, Nima
发明人： ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , MOKHLESI, Nima
IPC分类号： G11C11/56 , G11C16/26 , G06F11/10
CPC分类号： G11C16/34 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/3427 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as "Direct-Lookahead (DLA)".
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。当读取相对于第一组参考阈值时，获得硬比特。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中。

3. 发明申请

WO2011022386A1 SELECTIVE MEMORY CELL PROGRAM AND ERASE 审中-公开
标题翻译：选择性记忆细胞程序和删除
公开(公告)号：WO2011022386A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/045744
申请日：2010-08-17
申请人： SANDISK CORPORATION , DONG, Yingda , KUO, Tien-chien , HEMINK, Gerrit Jan
发明人： DONG, Yingda , KUO, Tien-chien , HEMINK, Gerrit Jan
IPC分类号： G11C16/16 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C2211/5641
摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.
摘要翻译：本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。之后，只有奇数字线被编程。数据可以被传送到在擦除之前存储多个存储单元的位的块。在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

4. 发明申请

WO2012087803A2 NON-VOLATILE MEMORY AND METHODS WITH READING SOFT BITS IN NON UNIFORM SCHEMES 审中-公开
标题翻译：非易失性存储器和非均匀程序读取软件位置的方法
公开(公告)号：WO2012087803A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/065429
申请日：2011-12-16
申请人： SANDISK IL LTD. , ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , KOH, Yee Lih
发明人： ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , KOH, Yee Lih
IPC分类号： G11C11/56
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5642 , G11C29/00 , G11C2029/0411
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。第二组的参考阈值被设置为在阈值窗口上不均匀地分布，以便在指定区域提供更高的分辨率。同时，它们有助于读取组中的软位，通过简单的算法和读取电路并使用最少的数据锁存器逐位读取。这是通过放宽第一组参考阈值是第二组的子集并且所得到的软比特关于硬比特对称分布的要求来实现的。

5. 发明申请

WO2012087805A2 NON-VOLATILE MEMORY AND METHODS WITH ASYMMETRIC SOFT READ POINTS AROUND HARD READ POINTS 审中-公开
标题翻译：具有非对称软读取点的非易失性存储器和方法硬读取点
公开(公告)号：WO2012087805A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/065443
申请日：2011-12-16
申请人： SANDISK IL LTD. , ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , KOH, Yee Lih
发明人： ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , KOH, Yee Lih
IPC分类号： G11C11/56 , G11C16/26 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1072 , G11C16/26 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.
摘要翻译：非易失性存储器使其单元的阈值被编程在第一组电压带中的第一组电压带内，该第一组电压带由阈值窗口上的第一组参考阈值划分。以相对于第二组参考阈值的较高分辨率读取单元以提供用于纠错的附加软比特。第二组的参考阈值被设置为在阈值窗口上不均匀分布，以便在指定区域提供更高的分辨率。同时，它们有利于以软件位的组读出，以便通过简单的算法和读取电路系统地逐位读取并使用最少数据锁存器。这是通过放宽第一组参考阈值是第二组子集并且所得到的软比特关于硬比特对称分布的要求来实现的。

6. 发明申请

WO2010151428A1 DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：检测完成非易失性存储的编程
公开(公告)号：WO2010151428A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/037846
申请日：2010-06-08
申请人： SANDISK CORPORATION , HEMINK, Gerrit Jan
发明人： HEMINK, Gerrit Jan
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations (Vva, Vvb, Vvc) are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non volatile storage elements that have not reached a condition (VvIc) that is different (e.g., lower) than the target level.
摘要翻译：对一组非易失性存储元件进行编程处理以便存储数据。在编程过程中，执行一个或多个验证操作（Vva，Vvb，Vvc）以确定非易失性存储元件是否已经达到其目标条件以存储适当的数据。当所有非易失性存储元件已经达到其目标电平或者尚未达到其目标电平的非易失性存储元件的数量小于可以使用错误校正处理来校正的数量或存储器单元时，可以停止编程在读取操作期间（或其他操作）。尚未达到其目标水平的非易失性存储元件的数量可以通过计数尚未达到比目标水平不同（例如较低）的条件（VvIc）的非易失性存储元件的数量来估计。

7. 发明申请

WO2007075180A1 FLASH MEMORY DEVICE COMPRISING A BOOSTER PLATE 审中-公开
标题翻译：包含加压板的闪存存储器件
公开(公告)号：WO2007075180A1
公开(公告)日：2007-07-05
申请号：PCT/US2006/005629
申请日：2006-02-17
申请人： SANDISK CORPORATION , FANG, Hao , PHAM, Tuan , HIGASHITANI, Masaaki , HEMINK, Gerrit Jan
发明人： PHAM, Tuan , HIGASHITANI, Masaaki , HEMINK, Gerrit Jan
IPC分类号： H01L27/115 , H01L27/105
CPC分类号： H01L27/11529 , G11C16/0483 , H01L27/105 , H01L27/11526
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自增强模式进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

8. 发明申请

WO2016069148A1 TWO-STROBE SENSING FOR NONVOLATILE STORAGE 审中-公开
标题翻译：用于非易失存储的双路感测
公开(公告)号：WO2016069148A1
公开(公告)日：2016-05-06
申请号：PCT/US2015/052077
申请日：2015-09-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUTTA, Deepanshu , MIAO, Xiaochang , HEMINK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5624
摘要： A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements.
摘要翻译：非易失性存储系统包括多个非易失性存储元件，连接到非易失性存储元件的多个位线，连接到非易失性存储元件的多个字线以及一个或多个控制电路连接到位线和字线。一个或多个控制电路对非易失性存储元件执行编程，验证，读取和擦除。当验证时，连接到非易失性存储元件的位线的第一子集被充电以允许感测，而位线的第二子集不被充电。当读取时，选择性地使用两个频闪检测处理来更准确地从非易失性存储元件读取数据。

9. 发明申请

WO2016069147A1 WORD LINE DEPENDENT TWO STROBE SENSING MODE FOR NONVOLATILE STORAGE ELEMENTS 审中-公开
标题翻译：非线性存储元件的字线相关的两个结构感测模式
公开(公告)号：WO2016069147A1
公开(公告)日：2016-05-06
申请号：PCT/US2015/052076
申请日：2015-09-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUTTA, Deepanshu , MIAO, Xiaochang , HEMINK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/26 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/3427
摘要： A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the nonvolatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the nonvolatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a one strobe sensing process or a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements, depending on whether the selected word line is within a threshold distance of a charging source for the selected bit lines.
摘要翻译：非易失性存储系统包括多个非易失性存储元件，连接到非易失性存储元件的多个位线，连接到非易失性存储元件的多个字线以及连接到非易失性存储元件的一个或多个控制电路位线和字线。一个或多个控制电路对非易失性存储元件执行编程，验证，读取和擦除。当验证时，连接到非易失性存储元件的位线的第一子集被充电以允许感测，而位线的第二子集不被充电。当读取时，根据所选择的字线是否在所选择的位的充电源的阈值距离内，选择性地使用一个选通感测处理或两个选通感测处理以更准确地从非易失性存储元件读取数据线。

10. 发明授权

EP2074630B1 CONTROLLED BOOSTING IN NON-VOLATILE MEMORY SOFT PROGRAMMING 有权
标题翻译：受控拉动了非挥发性存储器软编程
公开(公告)号：EP2074630B1
公开(公告)日：2013-01-23
申请号：EP07845063.2
申请日：2007-11-12
申请人： SanDisk Technologies Inc.
发明人： HEMINK, Gerrit Jan
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3427

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