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1. 发明申请

WO2016069148A1 TWO-STROBE SENSING FOR NONVOLATILE STORAGE 审中-公开
标题翻译：用于非易失存储的双路感测
公开(公告)号：WO2016069148A1
公开(公告)日：2016-05-06
申请号：PCT/US2015/052077
申请日：2015-09-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUTTA, Deepanshu , MIAO, Xiaochang , HEMINK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5624
摘要： A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements.
摘要翻译：非易失性存储系统包括多个非易失性存储元件，连接到非易失性存储元件的多个位线，连接到非易失性存储元件的多个字线以及一个或多个控制电路连接到位线和字线。一个或多个控制电路对非易失性存储元件执行编程，验证，读取和擦除。当验证时，连接到非易失性存储元件的位线的第一子集被充电以允许感测，而位线的第二子集不被充电。当读取时，选择性地使用两个频闪检测处理来更准确地从非易失性存储元件读取数据。

2. 发明申请

WO2014137846A1 DEFECT OR PROGRAM DISTURB DETECTION WITH FULL DATA RECOVERY CAPABILITY 审中-公开
标题翻译：缺陷或程序干扰检测具有完整的数据恢复能力
公开(公告)号：WO2014137846A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/019730
申请日：2014-03-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUTTA, Deepanshu , LEE, Dana , LI, Yan , SHAH, Grishma , MOOGAT, Farookh , HIGASHITANI, Masaaki
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C2211/5621 , G11C2211/5642
摘要： A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.
摘要翻译：用于一组非易失性存储元件的编程操作在程序验证测试通过并且发出程序状态=通过之后确定存储元件是否已经被正确编程。使用可选的一个或多个重建读取操作的逻辑运算，从与存储元件相关联的锁存器组重建写入数据。还执行正常读取操作以获得读取数据。确定读取数据和重建的写入数据之间的一些不匹配，并且基于不匹配的数量确定是否需要重写写入数据。

3. 发明申请

WO2014107346A1 ERASE FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：消除非易失性存储
公开(公告)号：WO2014107346A1
公开(公告)日：2014-07-10
申请号：PCT/US2013/077051
申请日：2013-12-20
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DUTTA, Deepanshu
发明人： OOWADA, Ken , DUTTA, Deepanshu
IPC分类号： G11C16/34 , G11C16/14 , G11C16/04 , G11C11/56
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3418
摘要： Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the word lines may be held at a low voltage (e.g., close to OV). However, the voltage applied to an edge word may be increased in magnitude relative to a previous voltage applied to the edge word line for at least a portion of the sequence of erase voltages. The edge word line could be the word line that is immediately adjacent to the select line. The increasing voltage applied to the edge word line may prevent or reduce damage to oxides between the select line and edge word line. It may also help to regulate the e-field across a tunnel oxide of memory cells on the edge word line.
摘要翻译：本文公开了用于擦除非易失性存储元件的技术。增加的擦除电压的序列可以施加到衬底。选择线可以浮动，并且许多字线可以保持在低电压（例如，接近0V）。然而，对于擦除电压序列的至少一部分，施加到边缘字的电压可以相对于施加到边缘字线的先前电压的幅度增加。边缘字线可以是紧邻选择线的字线。施加到边缘字线的增加的电压可以防止或减少对选择线和边缘字线之间的氧化物的损害。它也可以帮助调节边缘字线上的存储器单元的隧道氧化物的电场。

4. 发明申请

WO2012087410A1 ALTERNATE BIT LINE BIAS DURING PROGRAMMING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY 审中-公开
标题翻译：编程期间的替代位线偏移，以减少存储器中的通道到浮动栅极耦合
公开(公告)号：WO2012087410A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/056144
申请日：2011-10-13
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C16/24 , G11C16/34
CPC分类号： G11C16/24 , G11C16/3418 , G11C16/3436
摘要： In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure.
摘要翻译：在非易失性存储系统中，通过减少相邻存储元件在接近相同的编程脉冲时达到锁定状态的可能性来降低电容耦合效应。诸如提升的位线电压之类的减速措施被施加到与奇数位线相关联的字线的存储元件，而不是与与偶数位线相关联的存储元件。升高的位线电压施加在编程脉冲的范围上，然后通过一个或多个编程脉冲降压到地。施加减速措施的编程脉冲的范围可以自适应地固定或确定。当位线电压降低时，程序脉冲增量可以下降，然后增加。被编程为最高目标数据状态的存储元件可以从减速测量中排除。

5. 发明申请

WO2012018765A1 NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器中的自然阈值电压分配压缩
公开(公告)号：WO2012018765A1
公开(公告)日：2012-02-09
申请号：PCT/US2011/046197
申请日：2011-08-02
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back- and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower- programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.
摘要翻译：在非易失性存储器系统中，基于速度的编程速度减慢测量例如升高的位线被应用于更快编程的存储元件。执行使用来回字线顺序的多相编程操作，其中编程速度数据被存储在一个编程阶段的锁存器中，并且从锁存器读取以用于给定字线的后续编程阶段。可以通过检测多个存储元件何时达到指定的验证电平，计数基于存储元件的自然阈值电压分布而设置的附加数量的编程脉冲，然后执行一种分离更快和慢速编程存储元件的读取操作。可以在不同的编程阶段调整漏极侧选择栅极电压，以适应不同的位线偏置电平。

6. 发明申请

WO2015134702A1 COMPENSATING SOURCE SIDE RESISTANCE VERSUS WORD LINE 审中-公开
标题翻译：补偿源电阻VERSUS字线
公开(公告)号：WO2015134702A1
公开(公告)日：2015-09-11
申请号：PCT/US2015/018875
申请日：2015-03-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： TSENG, Huai-Yuan , LEE, Dana , LEE, Shih-Chung , DUTTA, Deepanshu , HAZEGHI, Arash
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/3459
摘要： A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.
摘要翻译：提供了一种方法和非易失性存储系统，其中施加到NAND串的源极的电压取决于被选择用于感测的非易失性存储元件的位置。这可以在不对NAND串进行体偏置的情况下完成。施加到NAND串的源极的电压的大小取决于所选择的存储器单元的位置（没有任何主体偏置）有助于减轻依赖于在一个实施例的感测操作期间选择哪个字线的故障。另外，读通道电压的幅度可以取决于源极线电压或所选存储器单元的位置。

7. 发明申请

WO2013096564A1 NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE 审中-公开
标题翻译：具有三层浮动门的非挥发性储存系统
公开(公告)号：WO2013096564A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/070833
申请日：2012-12-20
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , HIGAHSITANI, Masaaki , ZHAO, Dengtao , LEE, Sanghyun
发明人： DUTTA, Deepanshu , SATO, Shinji , HIGAHSITANI, Masaaki , ZHAO, Dengtao , LEE, Sanghyun
IPC分类号： H01L21/28 , H01L29/788 , G11C16/04 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： G11C16/10 , G11C16/0483 , H01L21/28273 , H01L27/11524 , H01L29/66825 , H01L29/788 , H01L29/7887
摘要： A non-volatile storage system includes memory cells with floating gates (104FG) that comprises three layers separated by two dielectric layers, an upper dielectric layer (UDL) and a lower dielectric layer (LDL). The dielectric layers may be oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate, near the interface between floating gate and tunnel dielectric (TD), while the upper dielectric layer is close to top of the floating gate, near the interface between floating gate and inter-gate dielectric (IGD).
摘要翻译：非易失性存储系统包括具有浮动栅极（104FG）的存储单元，其包括由两个电介质层分离的三层，上介电层（UDL）和下介电层（LDL）。电介质层可以是氧化物层，氮化物层，氧化物和氮化物的组合，或一些其它合适的电介质材料。下电介质层靠近浮动栅极的底部，靠近浮动栅极和隧道电介质（TD）之间的界面，而上部介电层靠近浮动栅极的顶部，靠近浮动栅极和沟道间介质之间的界面，栅极电介质（IGD）。

8. 发明授权

EP2831884B1 NONVOLATILE MEMORY PROGRAMMING WITH STRING SELECT TRANSISTOR GATE VOLTAGE DEPENDENT ON LOCATION OF SELECTED WORD LINE 有权转让
标题翻译：的选定字线电压依赖一个游戏程序中的
公开(公告)号：EP2831884B1
公开(公告)日：2016-05-11
申请号：EP12798123.1
申请日：2012-11-27
申请人： SanDisk Technologies, Inc.
发明人： LAI, Chun-hung , DUTTA, Deepanshu , SATO, Shinji , HEMIMK, Gerrit Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10

9. 发明授权

EP2499641B1 DATA STATE-DEPENDENT CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY 失效转让
标题翻译：数据状态于信道增益减少槽道到浮栅和功耗内存
公开(公告)号：EP2499641B1
公开(公告)日：2013-11-06
申请号：EP10784614.9
申请日：2010-11-10
申请人： SanDisk Technologies, Inc.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , SHAH, Grishma
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427

10. 发明公开

EP2462590A1 PROGRAMMING MEMORY WITH REDUCED PASS VOLTAGE DISTURB AND FLOATING GATE TO-CONTROL GATE LEAKAGE 有权转让
标题翻译：与降低的通过电压果酱和浮动栅极到控制栅极泄漏编程存储器
公开(公告)号：EP2462590A1
公开(公告)日：2012-06-13
申请号：EP10742064.8
申请日：2010-08-03
申请人： SanDisk Technologies, Inc.
发明人： DUTTA, Deepanshu , CHIN, Henry
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn-I neighbor storage element, and applying an optimal pass voltage to WLn-I for each group. Initially, the states of the storage elements on WLn-I are read. A program iteration includes multiple program pulses. A first program pulse (1402) is applied to WLn while a first pass voltage (1425) is applied to WLn-1, a first group (1480, 1482, 1488) of WLn storage elements is selected for programming, and a second group (1484, 1486) of WLn storage elements is inhibited. Next, a second program pulse (1404) is applied to WLn while a second pass voltage (1426) is applied to WLn-I, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states (A, B, C, E).

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