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1. 发明申请

WO2011123279A1 EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE -VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE 审中-公开
标题翻译：经过擦除后，可以除去感应深度电压阈值以外的额外的擦除脉冲
公开(公告)号：WO2011123279A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/029240
申请日：2011-03-21
申请人： SANDISK CORPORATION , OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
发明人： OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/34 , G11C16/14
CPC分类号： G11C11/5635 , G11C16/14 , G11C16/3436
摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses (1502, 1504, 1506, 1508, 1602, 1604) to a substrate, where each erase pulse is followed by a verify operation (1512, 1514, 1516, 1518, 1608). The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached (Verase-max), at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes (1610). The second phase applies one or more extra erase pulses (1606) which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write -erase endurance, while still achieving the desired deep erase.
摘要翻译：用于非易失性存储器的擦除操作包括第一和第二相。第一阶段将一系列电压脉冲（1502,1504,1506,1508,1602,1604）施加到衬底，其中每个擦除脉冲后跟验证操作（1512,1514,1516,1518,1608）。验证操作使用从最终期望的阈值电压电平偏移的验证电平。擦除脉冲以幅度升高直到达到最大电平（Verase-max），此时应用最大电平的附加擦除脉冲。当验证操作通过时，第一阶段结束（1610）。第二阶段施加一个或多个额外的擦除脉冲（1606），其在第一阶段中的幅度高于最后一个擦除脉冲，并且后面没有验证操作。这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写入耐久性，同时仍然实现期望的深度擦除。

2. 发明申请

WO2014003887A1 OPTIMIZED ERASE OPERATION FOR NON-VOLATILE MEMORY WITH PARTIALLY PROGRAMMED BLOCK 审中-公开
标题翻译：具有部分编程块的非易失性存储器的优化擦除操作
公开(公告)号：WO2014003887A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/039299
申请日：2013-05-02
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , OOWADA, Ken , NISHIMURA, Koichi , DONG, Yingda
发明人： DUTTA, Deepanshu , OOWADA, Ken , NISHIMURA, Koichi , DONG, Yingda
IPC分类号： G11C16/16 , G11C16/34 , G11C11/56
CPC分类号： G11C11/5635 , G11C16/16 , G11C16/344
摘要： In connection with an erase operation (800) of a block of nonvolatile storage elements, a determination is made as to whether the block is partially but not fully programmed (802). A degree of partial programming(804) can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed (814). In another approach, the block can be programmed before being erased (806, 808). Or, an extra erase pulse which is not followed by an erase-verify test can be applied (810, 812).
摘要翻译：结合非易失性存储元件块的擦除操作（800），确定块是否部分地但未被完全编程（802）。可以通过确定最高编程字线的预擦除读取操作来确定部分编程（804）的程度，或者确定在源侧字的小子集之上的字线子集中是否存在编程存储元件线。由于部分编程的块将比完全编程的块更容易通过擦除验证测试，因此采取措施确保块被深度擦除。在一种方法中，通过在块被部分编程时调整感测参数（814），擦除验证测试变得更严格。在另一种方法中，块可以在被擦除之前被编程（806,808）。或者，可以应用不伴随擦除验证测试的额外擦除脉冲（810,812）。

3. 发明申请

WO2009158350A1 IMPROVED PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 审中-公开
标题翻译：改进的编程算法，减少距离最小的额外罚款
公开(公告)号：WO2009158350A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048311
申请日：2009-06-23
申请人： SANDISK CORPORATION , LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
发明人： LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

4. 发明申请

WO2011025731A1 PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES 审中-公开
标题翻译：使用浮动位线的非易失性存储器的部分速度和全速编程
公开(公告)号：WO2011025731A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046312
申请日：2010-08-23
申请人： SANDISK CORPORATION , MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
发明人： MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed (fine) and full speed (coarse) programming are achieved for a non-volatile memory system. During a program operation, in a first time period (tl-t3), bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed (fine programming) and bit lines of storage elements to be programmed at a full speed (coarse programming) are fixed at ground potential. In a second time period (t4-t5), the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain grounded. In a third time period (t5-t8), the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：对于非易失性存储器系统，实现了部分速度（精细）和全速（粗略）编程。在编程操作期间，在第一时间段（t1-t3）中，要禁止的存储元件的位线被预充电，而要以部分速度（精细编程）编程的存储元件的位线和位线以全速编程的存储元件（粗略编程）固定在地电位。在第二时间段（t4-t5）中，以部分速度编程的存储元件的位线被驱动得较高，而要被禁止的存储元件的位线被浮置，并且存储元件的位线被编程保持接地。在第三时间段（t5-t8）中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

5. 发明申请

WO2010017013A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：WO2010017013A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/050974
申请日：2009-07-17
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻存储元件。

6. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

7. 发明申请

WO2011133404A1 PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS 审中-公开
标题翻译：编程非易失性存储包括减少其他记忆细胞的影响
公开(公告)号：WO2011133404A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032575
申请日：2011-04-14
申请人： SANDISK CORPORATION , DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
发明人： DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

8. 发明申请

WO2012128914A1 NONVOLATILE MEMORY AND METHOD FOR IMPROVED PROGRAMMING WITH REDUCED VERIFY 审中-公开
标题翻译：非易失性存储器和用于改进编程的方法，具有降低的验证
公开(公告)号：WO2012128914A1
公开(公告)日：2012-09-27
申请号：PCT/US2012/027471
申请日：2012-03-02
申请人： SANDISK TECHNOLOGIES INC. , DONG, Yingda , OOWADA, Ken , HSU, Cynthia
发明人： DONG, Yingda , OOWADA, Ken , HSU, Cynthia
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/10 , G11C16/3468
摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V 1 ,..., V N ). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value V i among the set by a predetermined margin. The overshoot of each memory cell when programmed past V i , to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
摘要翻译：非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。存储器状态由一组增加的分界阈值（V1，...，VN）划分。最初在编程过程中，相对于测试参考阈值验证存储器单元。该测试参考阈值具有通过预定余量的集合中的指定分界阈值V i的值偏移。可以确定当通过V i编程时每个存储单元的过冲大于或小于余量。因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

9. 发明申请

WO2013126109A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：WO2013126109A1
公开(公告)日：2013-08-29
申请号：PCT/US2012/066909
申请日：2012-11-28
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
发明人： OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
IPC分类号： G11C29/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

10. 发明申请

WO2007143399A3 NAND FLASH VERIFY METHOD WITH DIFFERENT COMPENSATED PASS VOLTAGES 审中-公开
公开(公告)号：WO2007143399A3
公开(公告)日：2007-12-13
申请号：PCT/US2007/069590
申请日：2007-05-23
申请人： SANDISK CORPORATION , MOKHLESI, Nima , DONG, Yingda
发明人： MOKHLESI, Nima , DONG, Yingda
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56
摘要： Errors can occur when reading the threshold voltage of a programmed non- volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

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