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1. 发明申请

WO2007143399A3 NAND FLASH VERIFY METHOD WITH DIFFERENT COMPENSATED PASS VOLTAGES 审中-公开
公开(公告)号：WO2007143399A3
公开(公告)日：2007-12-13
申请号：PCT/US2007/069590
申请日：2007-05-23
申请人： SANDISK CORPORATION , MOKHLESI, Nima , DONG, Yingda
发明人： MOKHLESI, Nima , DONG, Yingda
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56
摘要： Errors can occur when reading the threshold voltage of a programmed non- volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

2. 发明申请

WO2009158350A1 IMPROVED PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 审中-公开
标题翻译：改进的编程算法，减少距离最小的额外罚款
公开(公告)号：WO2009158350A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048311
申请日：2009-06-23
申请人： SANDISK CORPORATION , LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
发明人： LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

3. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

4. 发明申请

WO2011123279A1 EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE -VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE 审中-公开
标题翻译：经过擦除后，可以除去感应深度电压阈值以外的额外的擦除脉冲
公开(公告)号：WO2011123279A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/029240
申请日：2011-03-21
申请人： SANDISK CORPORATION , OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
发明人： OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/34 , G11C16/14
CPC分类号： G11C11/5635 , G11C16/14 , G11C16/3436
摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses (1502, 1504, 1506, 1508, 1602, 1604) to a substrate, where each erase pulse is followed by a verify operation (1512, 1514, 1516, 1518, 1608). The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached (Verase-max), at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes (1610). The second phase applies one or more extra erase pulses (1606) which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write -erase endurance, while still achieving the desired deep erase.
摘要翻译：用于非易失性存储器的擦除操作包括第一和第二相。第一阶段将一系列电压脉冲（1502,1504,1506,1508,1602,1604）施加到衬底，其中每个擦除脉冲后跟验证操作（1512,1514,1516,1518,1608）。验证操作使用从最终期望的阈值电压电平偏移的验证电平。擦除脉冲以幅度升高直到达到最大电平（Verase-max），此时应用最大电平的附加擦除脉冲。当验证操作通过时，第一阶段结束（1610）。第二阶段施加一个或多个额外的擦除脉冲（1606），其在第一阶段中的幅度高于最后一个擦除脉冲，并且后面没有验证操作。这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写入耐久性，同时仍然实现期望的深度擦除。

5. 发明申请

WO2011005401A2 REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：减少编程脉冲宽度以增强非易失性存储器的通道提升
公开(公告)号：WO2011005401A2
公开(公告)日：2011-01-13
申请号：PCT/US2010/037839
申请日：2010-06-08
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W.
发明人： DONG, Yingda , LUTZE, Jeffrey, W.
IPC分类号： G11C16/10
CPC分类号： G11C16/10
摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of storage elements to a trigger state. The switchover point occurs sooner for higher temperatures, and for drain side word lines. The trigger state can be selected based on temperature. A portion of storage elements which are required to reach the trigger state to trigger a switchover can also be set a function of temperature. Programming pulses of a shorter duration improve channel boosting for inhibited storage elements, thereby reducing program disturb for these storage elements.
摘要翻译：在编程操作期间，通过从使用较长持续时间的编程脉冲切换到在编程操作中途的较短持续时间的编程脉冲的切换，在非易失性存储系统中减少了编程干扰。切换点可以基于温度，所选字线位置和/或将存储元件跟踪到触发状态。对于较高的温度以及对于漏极侧字线，切换点更快发生。触发状态可以根据温度进行选择。达到触发状态以触发切换所需的存储元件的一部分也可以被设置为温度的函数。持续时间较短的编程脉冲可改善受抑制存储元件的通道升压，从而减少这些存储元件的编程干扰。

6. 发明申请

WO2009143435A1 ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：增强非易失性存储器中的通道增强的双线预先计费方案
公开(公告)号：WO2009143435A1
公开(公告)日：2009-11-26
申请号：PCT/US2009/044999
申请日：2009-05-22
申请人： SANDISK CORPORATION , DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间预充电位线。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

7. 发明申请

WO2010151427A1 FORECASTING PROGRAM DISTURB IN MEMORY BY DETECTING NATURAL THRESHOLD VOLTAGE DISTRIBUTION 审中-公开
标题翻译：通过检测自然阈值电压分配来预测存储器中的程序干扰
公开(公告)号：WO2010151427A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/037842
申请日：2010-06-08
申请人： SANDISK CORPORATION , DONG, Yingda , HSU, Cynthia
发明人： DONG, Yingda , HSU, Cynthia
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3454 , G11C7/04 , G11C11/5628 , G11C16/3418
摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb (1404) and taking a corresponding precautionary measure (1406, 1408, 1410, 1412), if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N1 and a number N2>N1 of the storage elements to reach the particular state. Temperature and word line position can also be used to determine the susceptibility to program disturb. A precautionary measure (1415) can involve using a higher pass voltage (1416), or abandoning programming of an upper page of data (1418) or an entire block( (1420). In some cases, programming continues with no precautionary measure (1414).
摘要翻译：如果需要，通过确定一组存储元件对编程干扰的敏感性（1404）和采取相应的预防措施（1406,1408,1410,1412），在编程操作期间在非易失性存储系统中减少编程干扰，以减少编程干扰发生的可能性。在下一页数据的编程期间，通过对被编程到特定状态的存储元件进行跟踪，并且确定需要数量N1和数N2的多个编程脉冲来确定该组存储元件的自然阈值电压分布 > N1的存储元素达到特定状态。温度和字线位置也可用于确定编程干扰的敏感度。预防措施（1415）可以涉及使用较高的通过电压（1416），或者放弃对数据的上页（1418）或整个块（（1420））的编程。在某些情况下，编程继续而不采取预防措施（1414 ）。

8. 发明申请

WO2008083221A2 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES 审中-公开
标题翻译：通过使用不同的预充电使能电压来编程具有减少程序故障的非易失性存储器
公开(公告)号：WO2008083221A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088947
申请日：2007-12-27
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
发明人： HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
IPC分类号： G11C16/12
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5628 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.
摘要翻译：未编程的非易失性存储元件组在编程期间升压，以减少或消除连接到所选字线的目标但未选定的存储单元的编程干扰。在将编程电压施加到所选字线并提升未选定组之前，未选定组被预充电以通过为未选定组提供更大的提升电位来进一步减少或消除编程干扰。在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

9. 发明申请

WO2011081910A1 PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP 审中-公开
标题翻译：使用快速检测和验证跳过编程非易失性存储
公开(公告)号：WO2011081910A1
公开(公告)日：2011-07-07
申请号：PCT/US2010/060221
申请日：2010-12-14
申请人： SANDISK CORPORATION , CHEN, Changyuan , LUTZE, Jeffrey , DONG, Yingda , HSU, Hua-ling
发明人： CHEN, Changyuan , LUTZE, Jeffrey , DONG, Yingda , HSU, Hua-ling
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G10L15/26 , G11C2211/5621
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non¬ volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.
摘要翻译：对一组非易失性存储元件进行编程处理以便存储数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

10. 发明申请

WO2011025731A1 PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES 审中-公开
标题翻译：使用浮动位线的非易失性存储器的部分速度和全速编程
公开(公告)号：WO2011025731A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046312
申请日：2010-08-23
申请人： SANDISK CORPORATION , MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
发明人： MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed (fine) and full speed (coarse) programming are achieved for a non-volatile memory system. During a program operation, in a first time period (tl-t3), bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed (fine programming) and bit lines of storage elements to be programmed at a full speed (coarse programming) are fixed at ground potential. In a second time period (t4-t5), the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain grounded. In a third time period (t5-t8), the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：对于非易失性存储器系统，实现了部分速度（精细）和全速（粗略）编程。在编程操作期间，在第一时间段（t1-t3）中，要禁止的存储元件的位线被预充电，而要以部分速度（精细编程）编程的存储元件的位线和位线以全速编程的存储元件（粗略编程）固定在地电位。在第二时间段（t4-t5）中，以部分速度编程的存储元件的位线被驱动得较高，而要被禁止的存储元件的位线被浮置，并且存储元件的位线被编程保持接地。在第三时间段（t5-t8）中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

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