专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012128914A1 NONVOLATILE MEMORY AND METHOD FOR IMPROVED PROGRAMMING WITH REDUCED VERIFY 审中-公开
标题翻译：非易失性存储器和用于改进编程的方法，具有降低的验证
公开(公告)号：WO2012128914A1
公开(公告)日：2012-09-27
申请号：PCT/US2012/027471
申请日：2012-03-02
申请人： SANDISK TECHNOLOGIES INC. , DONG, Yingda , OOWADA, Ken , HSU, Cynthia
发明人： DONG, Yingda , OOWADA, Ken , HSU, Cynthia
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/10 , G11C16/3468
摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V 1 ,..., V N ). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value V i among the set by a predetermined margin. The overshoot of each memory cell when programmed past V i , to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
摘要翻译：非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。存储器状态由一组增加的分界阈值（V1，...，VN）划分。最初在编程过程中，相对于测试参考阈值验证存储器单元。该测试参考阈值具有通过预定余量的集合中的指定分界阈值V i的值偏移。可以确定当通过V i编程时每个存储单元的过冲大于或小于余量。因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

2. 发明申请

WO2014003887A1 OPTIMIZED ERASE OPERATION FOR NON-VOLATILE MEMORY WITH PARTIALLY PROGRAMMED BLOCK 审中-公开
标题翻译：具有部分编程块的非易失性存储器的优化擦除操作
公开(公告)号：WO2014003887A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/039299
申请日：2013-05-02
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , OOWADA, Ken , NISHIMURA, Koichi , DONG, Yingda
发明人： DUTTA, Deepanshu , OOWADA, Ken , NISHIMURA, Koichi , DONG, Yingda
IPC分类号： G11C16/16 , G11C16/34 , G11C11/56
CPC分类号： G11C11/5635 , G11C16/16 , G11C16/344
摘要： In connection with an erase operation (800) of a block of nonvolatile storage elements, a determination is made as to whether the block is partially but not fully programmed (802). A degree of partial programming(804) can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed (814). In another approach, the block can be programmed before being erased (806, 808). Or, an extra erase pulse which is not followed by an erase-verify test can be applied (810, 812).
摘要翻译：结合非易失性存储元件块的擦除操作（800），确定块是否部分地但未被完全编程（802）。可以通过确定最高编程字线的预擦除读取操作来确定部分编程（804）的程度，或者确定在源侧字的小子集之上的字线子集中是否存在编程存储元件线。由于部分编程的块将比完全编程的块更容易通过擦除验证测试，因此采取措施确保块被深度擦除。在一种方法中，通过在块被部分编程时调整感测参数（814），擦除验证测试变得更严格。在另一种方法中，块可以在被擦除之前被编程（806,808）。或者，可以应用不伴随擦除验证测试的额外擦除脉冲（810,812）。

3. 发明申请

WO2013126109A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：WO2013126109A1
公开(公告)日：2013-08-29
申请号：PCT/US2012/066909
申请日：2012-11-28
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
发明人： OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
IPC分类号： G11C29/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

4. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

5. 发明申请

WO2011123279A1 EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE -VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE 审中-公开
标题翻译：经过擦除后，可以除去感应深度电压阈值以外的额外的擦除脉冲
公开(公告)号：WO2011123279A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/029240
申请日：2011-03-21
申请人： SANDISK CORPORATION , OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
发明人： OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/34 , G11C16/14
CPC分类号： G11C11/5635 , G11C16/14 , G11C16/3436
摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses (1502, 1504, 1506, 1508, 1602, 1604) to a substrate, where each erase pulse is followed by a verify operation (1512, 1514, 1516, 1518, 1608). The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached (Verase-max), at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes (1610). The second phase applies one or more extra erase pulses (1606) which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write -erase endurance, while still achieving the desired deep erase.
摘要翻译：用于非易失性存储器的擦除操作包括第一和第二相。第一阶段将一系列电压脉冲（1502,1504,1506,1508,1602,1604）施加到衬底，其中每个擦除脉冲后跟验证操作（1512,1514,1516,1518,1608）。验证操作使用从最终期望的阈值电压电平偏移的验证电平。擦除脉冲以幅度升高直到达到最大电平（Verase-max），此时应用最大电平的附加擦除脉冲。当验证操作通过时，第一阶段结束（1610）。第二阶段施加一个或多个额外的擦除脉冲（1606），其在第一阶段中的幅度高于最后一个擦除脉冲，并且后面没有验证操作。这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写入耐久性，同时仍然实现期望的深度擦除。

6. 发明申请

WO2011133404A1 PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS 审中-公开
标题翻译：编程非易失性存储包括减少其他记忆细胞的影响
公开(公告)号：WO2011133404A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032575
申请日：2011-04-14
申请人： SANDISK CORPORATION , DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
发明人： DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

7. 发明申请

WO2010151427A1 FORECASTING PROGRAM DISTURB IN MEMORY BY DETECTING NATURAL THRESHOLD VOLTAGE DISTRIBUTION 审中-公开
标题翻译：通过检测自然阈值电压分配来预测存储器中的程序干扰
公开(公告)号：WO2010151427A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/037842
申请日：2010-06-08
申请人： SANDISK CORPORATION , DONG, Yingda , HSU, Cynthia
发明人： DONG, Yingda , HSU, Cynthia
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3454 , G11C7/04 , G11C11/5628 , G11C16/3418
摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb (1404) and taking a corresponding precautionary measure (1406, 1408, 1410, 1412), if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N1 and a number N2>N1 of the storage elements to reach the particular state. Temperature and word line position can also be used to determine the susceptibility to program disturb. A precautionary measure (1415) can involve using a higher pass voltage (1416), or abandoning programming of an upper page of data (1418) or an entire block( (1420). In some cases, programming continues with no precautionary measure (1414).
摘要翻译：如果需要，通过确定一组存储元件对编程干扰的敏感性（1404）和采取相应的预防措施（1406,1408,1410,1412），在编程操作期间在非易失性存储系统中减少编程干扰，以减少编程干扰发生的可能性。在下一页数据的编程期间，通过对被编程到特定状态的存储元件进行跟踪，并且确定需要数量N1和数N2的多个编程脉冲来确定该组存储元件的自然阈值电压分布 > N1的存储元素达到特定状态。温度和字线位置也可用于确定编程干扰的敏感度。预防措施（1415）可以涉及使用较高的通过电压（1416），或者放弃对数据的上页（1418）或整个块（（1420））的编程。在某些情况下，编程继续而不采取预防措施（1414 ）。

8. 发明申请

WO2013115900A1 REDUCING WEAK- ERASE TYPE READ DISTURB IN 3D NAND NON- VOLATILE MEMORY 审中-公开
标题翻译：减少3D NAND非易失性存储器中的弱读取干扰
公开(公告)号：WO2013115900A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/066460
申请日：2012-11-23
申请人： SANDISK TECHNOLOGIES, INC. , DONG, Yingda , MUI, Man, L. , MIWA, Hitoshi
发明人： DONG, Yingda , MUI, Man, L. , MIWA, Hitoshi
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non- conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.
摘要翻译：用于3D堆叠存储器件的读取过程为未选择的存储器串提供最佳级别的通道升压，以抑制正常和弱擦除类型的读取干扰。通过控制位线（Vbl），漏极侧选择栅极（Vsgd_unsel），源极选择栅极（Vsgs_unsel），存储器件的选定电平（字线层）（Vcg_sel）的电压，以及未选择的内存设备级别（Vcg_unsel）。通过初始使漏极侧和源极选择栅极不导通，可以提高通道，以允许来自增加的Vcg_unsel的电容耦合。然后通过升高Vsgd_unsel和/或Vsgs_unsel来使漏极侧和/或源极侧选择栅极导通，从而中断升压。另外，当Vcg_unsel仍在增加时，通过使漏极侧和/或源极侧选择栅极再次导通，可以发生升压。或者，通道可以在Vbl驱动。两级升压驱动Vbl上的通道，然后通过电容耦合提供升压。

9. 发明申请

WO2012170282A1 INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储器的读取电压的智能转换
公开(公告)号：WO2012170282A1
公开(公告)日：2012-12-13
申请号：PCT/US2012/040311
申请日：2012-05-31
申请人： SANDISK TECHNOLOGIES, INC. , YUAN, Jiahui , DONG, Yingda , KWONG, Charles
发明人： YUAN, Jiahui , DONG, Yingda , KWONG, Charles
IPC分类号： G11C11/56 , G11C16/34 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3454 , G11C16/349 , G11C29/021 , G11C29/028
摘要： A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.
摘要翻译：确定并优化循环存储器的第一个读通过电压。为一个或多个管芯确定一个或多个启动读通过电压。该系统基于编程/擦除擦除周期的数量，第一读取通过电压和相应的启动读取通过电压来动态地计算当前的读取通过电压。使用计算出的电流读通过电压从一个或多个非易失性存储元件读取数据。

10. 发明申请

WO2014066264A1 PRE-CHARGE DURING PROGRAMMIMG FOR 3RD MEMORY USING GATE- INDUCED DRAIN LEAKAGE 审中-公开
标题翻译：使用门控感应漏水泄漏的三维存储器程序期间的预付费
公开(公告)号：WO2014066264A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/065970
申请日：2013-10-21
申请人： SANDISK TECHNOLOGIES, INC , DUNGA, Mohan , DONG, Yingda , OU, Wendy
发明人： DUNGA, Mohan , DONG, Yingda , OU, Wendy
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C2213/71
摘要： In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre- charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.
摘要翻译：在3D堆叠非易失性存储器件的编程操作中，禁止的NAND串的通道由栅极引起漏极泄漏（GIDL）预充电，以实现高水平的升压，从而防止禁止的存储元件中的程序干扰。在程序验证迭代中，在施加编程脉冲之前，漏极侧选择栅极晶体管被反向偏置以产生GIDL，使得该通道被提升到诸如1.5V的预充电电平。随后，当将编程脉冲施加到所选择的字线并且将通过电压施加到未选字线时，由于电容耦合，该通道从预充电电平升高。即使对于被部分编程的NAND串也是有效的，因为它不依赖于从位线端直接驱动通道。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式