专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009143435A1 ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：增强非易失性存储器中的通道增强的双线预先计费方案
公开(公告)号：WO2009143435A1
公开(公告)日：2009-11-26
申请号：PCT/US2009/044999
申请日：2009-05-22
申请人： SANDISK CORPORATION , DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间预充电位线。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

2. 发明申请

WO2013158556A1 SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS 审中-公开
标题翻译：具有选择性抑制通过位置的3D非易失性存储器的软擦除操作
公开(公告)号：WO2013158556A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036615
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/16 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障比特。

3. 发明申请

WO2013126109A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：WO2013126109A1
公开(公告)日：2013-08-29
申请号：PCT/US2012/066909
申请日：2012-11-28
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
发明人： OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
IPC分类号： G11C29/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

4. 发明申请

WO2010077528A1 REGULATION OF RECOVERY RATES IN CHARGE PUMPS 审中-公开
标题翻译：充电泵中恢复率的调节
公开(公告)号：WO2010077528A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/066268
申请日：2009-12-01
申请人： SANDISK CORPORATION , MUI, Man Lung , LEE, Seungpil , NGUYEN, Hao Thai
发明人： MUI, Man Lung , LEE, Seungpil , NGUYEN, Hao Thai
IPC分类号： H02M3/07 , G11C5/14 , G11C16/30
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30
摘要： A method is presented of setting a frequency of a clock for a charge pump system including the clock and a charge pump. This includes setting an initial value for the frequency of the clock and, while operating the charge pump system using the clock running at the initial frequency value, determining the ramp rate of an output voltage for the charge pump during a recovery phase. The frequency of the clock is then adjusted so that the ramp rate of the output voltage for the charge pump during the recovery phase falls in a range not exceeding a predetermined maximum rate. A charge pump system is also described that includes a register having a settable value, where the charge pump clock frequency is responsive to the register value, and count and comparison circuitry is connectable to receive the pump's output voltage and the clock signal and determine from them the number of clock cycles the charge pump uses to recover from a reset value to a predetermined value.
摘要翻译：提出了一种设置包括时钟和电荷泵的电荷泵系统的时钟频率的方法。这包括设置时钟频率的初始值，并且在使用以初始频率值运行的时钟运行电荷泵系统的同时，在恢复阶段确定电荷泵的输出电压的斜坡率。然后调整时钟的频率，使得在恢复阶段期间电荷泵的输出电压的斜坡速率落在不超过预定最大速率的范围内。还描述了一种电荷泵系统，其包括具有可设置值的寄存器，其中电荷泵时钟频率响应于寄存器值，并且计数和比较电路可连接以接收泵的输出电压和时钟信号并从它们确定电荷泵用于从复位值恢复到预定值的时钟周期数。

5. 发明申请

WO2009085865A1 LOW NOISE SENSE AMPLIFIER ARRAY AND METHOD FOR NONVOLATILE MEMORY 审中-公开
标题翻译：低噪声感测放大器阵列和非易失性存储器的方法
公开(公告)号：WO2009085865A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/087262
申请日：2008-12-17
申请人： SANDISK CORPORATION , NGUYEN, Hao Thai , MUI, Man Lung , LEE, Seungpil
发明人： NGUYEN, Hao Thai , MUI, Man Lung , LEE, Seungpil
IPC分类号： G11C16/26 , G11C7/02 , G11C7/06
CPC分类号： G11C7/02 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/5642 , G11C16/26
摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.
摘要翻译：在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步检测，而页面中的其他单元继续被感测。被锁定的感测模块处于锁定模式并变为非活动状态。当处于锁定模式时，来自感测模块的噪声源变得显着。通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。

6. 发明申请

WO2008083132A3 COMPLETE WORD LINE LOOK AHEAD WITH EFFICIENT DATA LATCH ASSIGNMENT IN NON-VOLATILE MEMORY READ OPERATIONS 审中-公开
公开(公告)号：WO2008083132A3
公开(公告)日：2008-07-10
申请号：PCT/US2007/088779
申请日：2007-12-24
申请人： SANDISK CORPORATION , MUI, Man, Lung , LEE, Seungpil
发明人： MUI, Man, Lung , LEE, Seungpil
IPC分类号： G11C16/28
摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non- volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.

7. 发明申请

WO2014066263A1 DYNAMIC BIT LINE BIAS FOR PROGRAMMING NON-VOLATILE MEMORY 审中-公开
标题翻译：用于编程非易失性存储器的动态位线偏移
公开(公告)号：WO2014066263A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/065969
申请日：2013-10-21
申请人： SANDISK TECHNOLOGIES,INC. , DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C11/56 , G11C16/12 , G11C7/12 , G11C16/24
CPC分类号： G11C16/10 , G11C7/12 , G11C11/5628 , G11C16/12 , G11C16/24 , G11C16/3459
摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
摘要翻译：用于一组非易失性存储元件的程序操作。维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。可以使用不同的位线电压，具有公共的步长或不同的步长。结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。在缓慢编程模式下，锁存器保持相关存储元件所经历的编程脉冲计数。当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。

8. 发明申请

WO2013180893A1 THRESHOLD VOLTAGE ADJUSTMENT FOR A SELECT GATE TRANSISTOR IN A STACKED NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：堆叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
公开(公告)号：WO2013180893A1
公开(公告)日：2013-12-05
申请号：PCT/US2013/039505
申请日：2013-05-03
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C29/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

9. 发明申请

WO2013158557A1 ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT 审中-公开
标题翻译：具有可控门控感应漏水电流的3D非易失性存储器的擦除操作
公开(公告)号：WO2013158557A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036616
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/06 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate- induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以受益于更高的栅极引起的漏极泄漏（GIDL）电流以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

10. 发明申请

WO2010080674A1 SENSING CIRCUIT AND METHOD WITH REDUCED SUSCEPTIBILITY TO SPATIAL AND TEMPERATURE VARIATIONS 审中-公开
标题翻译：传感电路和降低对空间和温度变化的可靠性的方法
公开(公告)号：WO2010080674A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/069703
申请日：2009-12-29
申请人： SANDISK CORPORATION , DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/26
摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit (106) that includes a sensing device (104) and a sense transistor (287) coupled to the sensing device. A first switch (288) that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches (282, 293, 291, 289) that are coupled to the sensing device and to a target element (10). The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.
摘要翻译：公开了一种读出放大器。一个实施例是感测电路（106），其包括耦合到感测装置的感测装置（104）和感测晶体管（287）。耦合到感测晶体管和感测装置的第一开关（288）使得感测装置被充电到作为感测晶体管的阈值电压的函数的第一电压。耦合到感测装置和目标元件（10）的一个或多个第二开关（282,293,291,289）。第二开关将感测装置耦合到目标元件以修改感测装置上的第一电压，并且在将修改的第一电压施加到感测晶体管的感测阶段期间将目标元件与感测装置分离。目标元件的条件基于响应于将修改的第一电压施加到感测晶体管是否导通感测晶体管来确定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式