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1. 发明申请

WO2010117807A2 TWO PASS ERASE FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：两次擦拭非易失性存储
公开(公告)号：WO2010117807A2
公开(公告)日：2010-10-14
申请号：PCT/US2010/029246
申请日：2010-03-30
申请人： SANDISK CORPORATION , LEE, Dana , MOKHLESI, Nima , KHANDEL WAL, Anubhav
发明人： LEE, Dana , MOKHLESI, Nima , KHANDEL WAL, Anubhav
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C11/5635
摘要： Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells' threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.
摘要翻译：这里公开了用于擦除非易失性存储单元的技术。存储单元使用试擦除脉冲进行擦除。基于试擦除脉冲的大小和在试擦除后关于阈值电压分布收集的数据来确定第二脉冲的合适幅度。第二擦除脉冲用于擦除存储单元。在一个实现中，在第二擦除之后，存储器单元的阈值电压未被验证。可以执行第二次擦除之后的软编程。软编程脉冲的大小可以基于试擦除脉冲来确定。在一个实现中，在软编程之后，存储器单元的阈值电压不被验证。限制擦除脉冲和软编程脉冲的数量可节省时间和功耗。确定第二擦除脉冲的适当幅度可以最大限度地减少或消除过度擦除。

2. 发明申请

WO2009082637A1 REGULATION OF SOURCE POTENTIAL TO COMBAT CELL SOURCE IR DROP 审中-公开
标题翻译：源电位对调节细胞来源红细胞减少的调节
公开(公告)号：WO2009082637A1
公开(公告)日：2009-07-02
申请号：PCT/US2008/086694
申请日：2008-12-12
申请人： SANDISK CORPORATION , LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
发明人： LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
IPC分类号： G11C16/30
CPC分类号： G11C16/30
摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.
摘要翻译：提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。误差是由电流流动时芯片接地源极路径的电阻上的电压降引起的。为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元的结构块现在已经跑到地面上了。变化包括可在聚集节点和地之间连接的非线性电阻元件。

3. 发明申请

WO2009158350A1 IMPROVED PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 审中-公开
标题翻译：改进的编程算法，减少距离最小的额外罚款
公开(公告)号：WO2009158350A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048311
申请日：2009-06-23
申请人： SANDISK CORPORATION , LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
发明人： LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

4. 发明申请

WO2009042345A1 NAND STRINGS WITH OFFSET CHARGE STORAGE LAYERS AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有偏置电荷存储层的NAND带及其制造方法
公开(公告)号：WO2009042345A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/074641
申请日：2008-08-28
申请人： SANDISK CORPORATION , LUTZE, Jeffrey, W. , LEE, Dana
发明人： LUTZE, Jeffrey, W. , LEE, Dana
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/1158 , H01L27/11524 , H01L27/11553 , H01L27/11568 , H01L27/1157
摘要： A plurality of non- volatile storage elements on a common active layer are offset from neighbor non- volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. For example, a NAND string over active area (100) has a charge storage nitride layer (112) that is vertically offset to the charge storage layer (112) of the NAND string over active area (202).
摘要翻译：公共活动层上的多个非易失性存储元件偏离邻近非易失性存储元件。非易失性存储元件的这种抵消有助于减少邻近非易失性存储元件的干扰。还描述了制造偏移非易失性存储元件的制造方法。例如，有源区（100）上的NAND串具有电荷存储氮化物层（112），其在有源区（202）上垂直偏移到NAND串的电荷存储层（112）。

5. 发明申请

WO2010005878A1 DIELECTRIC CAP ABOVE FLOATING GATE 审中-公开
标题翻译：电磁盖上浮门
公开(公告)号：WO2010005878A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/049620
申请日：2009-07-02
申请人： SANDISK CORPORATION , LEE, Dana , CHIN, Henry , KAI, James , ORIMOTO, Takashi, Whitney , PURAYATH, Vinod, R. , MATAMIS, George
发明人： LEE, Dana , CHIN, Henry , KAI, James , ORIMOTO, Takashi, Whitney , PURAYATH, Vinod, R. , MATAMIS, George
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/265
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324
摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.
摘要翻译：公开了一种包括一组非易失性存储元件的存储器系统。给定的存储单元在浮动栅极上方具有电介质盖。在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。电介质盖减少了浮动栅极和控制栅极之间的漏电流。电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

6. 发明申请

WO2008083221A2 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES 审中-公开
标题翻译：通过使用不同的预充电使能电压来编程具有减少程序故障的非易失性存储器
公开(公告)号：WO2008083221A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088947
申请日：2007-12-27
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
发明人： HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
IPC分类号： G11C16/12
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5628 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.
摘要翻译：未编程的非易失性存储元件组在编程期间升压，以减少或消除连接到所选字线的目标但未选定的存储单元的编程干扰。在将编程电压施加到所选字线并提升未选定组之前，未选定组被预充电以通过为未选定组提供更大的提升电位来进一步减少或消除编程干扰。在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

7. 发明申请

WO2011133412A1 P-TYPE CONTROL GATE IN NON-VOLATILE STORAGE AND METHODS FOR FORMING SAME 审中-公开
标题翻译：非挥发性储存中的P型控制闸门及其形成方法
公开(公告)号：WO2011133412A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032635
申请日：2011-04-15
申请人： SANDISK CORPORATION , ORIMOTO, Takashi Whitney , SUYAMA, Atsushi , TIAN, Ming , CHIN, Henry , CHIEN, Henry , PURAYATH, Vinod Robert , LEE, Dana
发明人： ORIMOTO, Takashi Whitney , SUYAMA, Atsushi , TIAN, Ming , CHIN, Henry , CHIEN, Henry , PURAYATH, Vinod Robert , LEE, Dana
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/28 , H01L29/423
CPC分类号： H01L21/28291 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/788
摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.
摘要翻译：公开了非电压存储和用于制造非易失性存储器的技术。在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。在一个实施例中，控制栅极的下部是p型多晶硅。控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。因此，如果控制门耗尽，可能会发生的一些问题得到缓解。例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

8. 发明申请

WO2009032747A1 REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING 审中-公开
标题翻译：减少编程过程中干扰的影响
公开(公告)号：WO2009032747A1
公开(公告)日：2009-03-12
申请号：PCT/US2008/074621
申请日：2008-08-28
申请人： SANDISK CORPORATION , LEE, Dana , YERO, Emilio
发明人： LEE, Dana , YERO, Emilio
IPC分类号： G11C16/10 , G11C16/02 , G11C29/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

9. 发明申请

WO2008083214A1 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY REMOVING PRE-CHARG DEPENDENCY ON WORD LINE DATA 审中-公开
标题翻译：通过在字线数据上删除预先确定的程序来编程减少程序干扰的非易失性存储器
公开(公告)号：WO2008083214A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088931
申请日：2007-12-27
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
IPC分类号： G11C16/04 , G11C16/12 , G11C11/56
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.
摘要翻译：在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

10. 发明申请

WO2011008451A2 SYSTEM AND METHOD RESPONSIVE TO A RATE OF CHANGE OF A PERFORMANCE PARAMETER OF A MEMORY 审中-公开
标题翻译：系统和方法对记忆性能参数的变化率的影响
公开(公告)号：WO2011008451A2
公开(公告)日：2011-01-20
申请号：PCT/US2010/039710
申请日：2010-06-23
申请人： SANDISK CORPORATION , D'ABREU, Manuel, Antonio , SKALA, Stephen , LEE, Dana
发明人： D'ABREU, Manuel, Antonio , SKALA, Stephen , LEE, Dana
IPC分类号： G11C16/34
CPC分类号： G11C16/349 , G06F11/1068 , G11C29/76 , G11C2029/0411 , G11C2029/4402
摘要： Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold.
摘要翻译：公开了响应于存储器的性能参数的变化率的系统和方法。在特定实施例中，确定非易失性存储器的性能参数的变化率。将变化率与阈值进行比较，并且响应于确定变化率满足阈值来执行动作。

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