专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012109101A1 DATA RECOVERY USING ADDITIONAL ERROR CORRECTION CODING DATA 审中-公开
标题翻译：数据恢复使用附加错误修正编码数据
公开(公告)号：WO2012109101A1
公开(公告)日：2012-08-16
申请号：PCT/US2012/023735
申请日：2012-02-03
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1012
摘要： A method in a data storage device receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and a second sub-block of data. The method also includes initiating an ECC operation to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data block, first additional ECC data that is external to the data block is retrieved and a second ECC operation is initiated to process the first sub-block of data using the first additional ECC data.
摘要翻译：一种数据存储设备中的接收数据的方法，该数据包括用于数据块的数据块和主纠错编码（ECC）数据。数据块包括数据的第一子块和数据的第二子块。该方法还包括启动ECC操作以使用主ECC数据处理数据块。响应于指示数据块中的不可校正错误的ECC操作，检索在数据块外部的第一附加ECC数据，并且启动第二ECC操作以使用第一附加ECC数据来处理第一子数据块。

2. 发明申请

WO2011008451A2 SYSTEM AND METHOD RESPONSIVE TO A RATE OF CHANGE OF A PERFORMANCE PARAMETER OF A MEMORY 审中-公开
标题翻译：系统和方法对记忆性能参数的变化率的影响
公开(公告)号：WO2011008451A2
公开(公告)日：2011-01-20
申请号：PCT/US2010/039710
申请日：2010-06-23
申请人： SANDISK CORPORATION , D'ABREU, Manuel, Antonio , SKALA, Stephen , LEE, Dana
发明人： D'ABREU, Manuel, Antonio , SKALA, Stephen , LEE, Dana
IPC分类号： G11C16/34
CPC分类号： G11C16/349 , G06F11/1068 , G11C29/76 , G11C2029/0411 , G11C2029/4402
摘要： Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold.
摘要翻译：公开了响应于存储器的性能参数的变化率的系统和方法。在特定实施例中，确定非易失性存储器的性能参数的变化率。将变化率与阈值进行比较，并且响应于确定变化率满足阈值来执行动作。

3. 发明申请

WO2011002657A1 METHOD AND DEVICE FOR SELECTIVELY REFRESHING A REGION OF A MEMORY OF A DATA STORAGE DEVICE 审中-公开
标题翻译：用于选择性地刷新数据存储设备的存储器的区域的方法和设备
公开(公告)号：WO2011002657A1
公开(公告)日：2011-01-06
申请号：PCT/US2010/039708
申请日：2010-06-23
申请人： SANDISK CORPORATION , D'ABREU, Manuel, Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel, Antonio , SKALA, Stephen
IPC分类号： G06F11/00 , G06F11/10 , G11C11/4076
CPC分类号： G11C16/10 , G06F11/1068 , G11C16/3431
摘要： A method and device for selectively refreshing a region of a non volatile memory of a data storage device is disclosed. In a particular embodiment, a method is disclosed that includes comparing a time stamp received from a host device to a first time stamp retrieved from a data storage device for a first region of a non volatile memory, the first region including a least recently accessed region of a memory array within the data storage device. The method also includes selectively refreshing the first region based on a comparison of a difference between the time stamp received from the host device and the first time stamp as compared to a threshold, where the threshold is adjusted based on a first error count corresponding to a number of errors detected by an error correction code (ECC) engine with respect to data retrieved from the first region.
摘要翻译：公开了一种用于有选择地刷新数据存储装置的非易失性存储器的区域的方法和装置。在特定实施例中，公开了一种方法，其包括将从主机设备接收的时间标记与从非易失性存储器的第一区域的数据存储设备检索的第一时间标记进行比较，所述第一区域包括最近访问的区域的数据存储设备内的存储器阵列。该方法还包括基于从主机设备接收的时间戳和与阈值相比较的第一时间戳之间的差异的比较来选择性地刷新第一区域，其中基于对应于第一时间戳的第一错误计数来调整阈值由纠错码（ECC）引擎相对于从第一区域检索的数据检测到的错误的数量。

4. 发明申请

WO2013003181A1 SMART BRIDGE FOR MEMORY CORE 审中-公开
标题翻译：智能桥存储核心
公开(公告)号：WO2013003181A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/043465
申请日：2012-06-21
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen , PANTELAKIS, Dimitris , NAIR, Radhakrishnan , PANCHOLI, Deepak
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen , PANTELAKIS, Dimitris , NAIR, Radhakrishnan , PANCHOLI, Deepak
IPC分类号： G06F11/10 , G06F12/02 , G06F13/16
CPC分类号： G11C5/02 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G06F13/1668 , G11C14/0063 , G11C16/10 , G11C16/26 , G11C29/04 , G11C2029/0411 , Y02D10/14
摘要： An apparatus includes a first semiconductor device including a memory core, such as a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device may include a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller. Another apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.
摘要翻译：一种装置包括：第一半导体器件，包括诸如NAND闪速存储器核心的存储器核心。该装置还包括第二半导体器件，其包括与存储器核心相关联的外围电路。第二半导体器件可以包括耦合到存储器控制器的第一串行器/解串器通信接口的第二串行器/解串器通信接口。另一种装置包括第一存储器管芯，其包括第一存储器核心，包括第二存储器核心的第二存储器管芯以及耦合到第一存储器管芯和第二存储器管芯的外围管芯。周边裸片包括对应于第一存储器核心的外围电路和对应于第二存储器核心的外围电路。外围芯片响应于存储器控制器并被配置为在第一存储器核心处启动第一存储器操作，并且在第二存储器核心处启动第二存储器操作。

5. 发明申请

WO2011002656A1 SYSTEM AND METHOD OF TRACKING ERROR DATA WITHIN A STORAGE DEVICE 审中-公开
标题翻译：跟踪存储设备中的错误数据的系统和方法
公开(公告)号：WO2011002656A1
公开(公告)日：2011-01-06
申请号：PCT/US2010/039699
申请日：2010-06-23
申请人： SANDISK CORPORATION , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1076 , G06F11/1004
摘要： Systems and methods of tracking error data are disclosed. A method includes receiving a first checksum associated with error locations of a first error correction code operation and receiving a second checksum associated with error locations of a second error correction code operation. The first checksum is compared to the second checksum and an action is initiated on a region of a memory array based on a result of the comparison.
摘要翻译：公开了跟踪误差数据的系统和方法。一种方法包括：接收与第一纠错码操作的错误位置相关联的第一校验和，并接收与第二纠错码操作的错误位置相关联的第二校验和。将第一校验和与第二校验和进行比较，并且基于比较结果在存储器阵列的区域上发起动作。

6. 发明申请

WO2013039696A1 DATA STORAGE DEVICE AND METHOD TO CORRECT BIT VALUES USING MULTIPLE READ VOLTAGES 审中-公开
标题翻译：数据存储设备和使用多个读取电压校正位值的方法
公开(公告)号：WO2013039696A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/052889
申请日：2012-08-29
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10 , G11C16/34
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/52
摘要： A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.
摘要翻译：数据存储装置包括具有多个存储元件的存储器。存储器被配置为使用第一读取电压读取一组存储元件以获得第一多个位值。控制器耦合到存储器。控制器被配置为针对第一多个位值启动第一纠错码（ECC）过程。响应于第一ECC程序确定第一多个比特值不可校正，控制器还被配置为指示存储器使用第二读取电压读取该组存储元件以获得第二多个比特值，并且将所述第一多个比特值中的一个或多个值改变为所述第二多个比特值的对应值，以生成第一多个校正比特值。

7. 发明申请

WO2012057995A1 HYBRID ERROR CORRECTION CODING TO ADDRESS UNCORRECTABLE ERRORS 审中-公开
标题翻译：混合错误校正编码来解决不正确的错误
公开(公告)号：WO2012057995A1
公开(公告)日：2012-05-03
申请号：PCT/US2011/055739
申请日：2011-10-11
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data.
摘要翻译：存储装置中的方法包括接收数据块的数据块和主纠错编码（ECC）数据的数据。数据块包括数据的第一子块和对应于第一子块的第一ECC数据。启动ECC操作以使用主ECC数据来处理数据块。响应于指示数据中的不可校正错误的ECC操作，启动第一子块ECC操作以使用第一ECC数据处理第一子数据块。

8. 发明申请

WO2012054261A1 SYSTEM AND METHOD OF INTERLEAVING DATA ACCORDING TO AN ADJUSTABLE PARAMETER 审中-公开
标题翻译：根据可调整参数交换数据的系统和方法
公开(公告)号：WO2012054261A1
公开(公告)日：2012-04-26
申请号：PCT/US2011/055731
申请日：2011-10-11
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen , NARADASI, Jayaprakash , VENKITACHALAM, Anand
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen , NARADASI, Jayaprakash , VENKITACHALAM, Anand
IPC分类号： G06F11/10 , G11C11/56
CPC分类号： G06F11/1072 , G11C11/5621 , G11C11/5671
摘要： A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells.
摘要翻译：具有存储器的数据存储设备中的方法包括：接收要存储在存储器的单元组中的位值，并根据可调参数交织接收到的位值以形成多个交错数据位组。该方法还包括将多个交织的数据比特组写入该组小区。

9. 发明申请

WO2012044766A1 SYSTEM AND METHOD OF DATA ENCODING 审中-公开
标题翻译：数据编码的系统和方法
公开(公告)号：WO2012044766A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/053885
申请日：2011-09-29
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： A method includes reading data from a data area of a word line and reading first ECC data from an ECC area of the word line. The method also includes, in response to determining that an error indicator exceeds a threshold, storing second ECC data in the ECC area. The second ECC data corresponds to a subsection of the data area.
摘要翻译：一种方法包括从字线的数据区读取数据，并从字线的ECC区读取第一ECC数据。响应于确定错误指示符超过阈值，该方法还包括在ECC区域中存储第二ECC数据。第二ECC数据对应于数据区域的子部分。

10. 发明申请

WO2011094051A1 SYSTEM AND METHOD TO CORRECT DATA ERRORS USING A STORED COUNT OF BIT VALUES 审中-公开
标题翻译：使用存储的位值校正数据错误的系统和方法
公开(公告)号：WO2011094051A1
公开(公告)日：2011-08-04
申请号：PCT/US2011/020533
申请日：2011-01-07
申请人： SANDISK CORPORATION , D'ABREU, Manuel Antonio , SKALA, Stephen , GONZALEZ, Carlos Joseph
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen , GONZALEZ, Carlos Joseph
IPC分类号： G06F11/10
CPC分类号： G06F11/1072
摘要： At a controller coupled to a memory array, a method includes receiving an indication that a first group of data bits read from the memory array includes errors that are uncorrectable by an error correction coding (ECC) engine. A count of the first group of data bits having a particular bit value may be compared to a prior count of data bits having the particular bit value. In response to determining that the count exceeds the prior count, a bit of the first group of data bits that has the particular bit value and that corresponds to a same memory cell as a corrected data bit of a second group of data bits is identified. A value of the identified bit of the first group may be changed to generate an adjusted group of data bits that may be provided to the ECC engine.
摘要翻译：在耦合到存储器阵列的控制器上，一种方法包括接收从存储器阵列读取的第一组数据位包括由纠错编码（ECC）引擎不可校正的错误的指示。可以将具有特定位值的第一组数据位的计数与具有特定位值的数据位的先前计数进行比较。响应于确定计数超过先前计数，识别具有特定位值并且对应于与第二组数据位的校正数据位相同的存储器单元的第一组数据位的位。可以改变第一组的所识别的比特的值，以生成可以提供给ECC引擎的经调整的数据比特组。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式