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1. 发明授权

US08364458B2 Simulation program and simulation apparatus 有权
标题翻译：仿真程序和仿真设备
公开(公告)号：US08364458B2
公开(公告)日：2013-01-29
申请号：US12618137
申请日：2009-11-13
申请人： Ryo Kuya , Yasuki Nakamura , Tatsuya Yoshino
发明人： Ryo Kuya , Yasuki Nakamura , Tatsuya Yoshino
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F13/105 , G06F9/455
摘要： A simulation program stored in a computer readable recording medium to execute a simulation of first and second simulation objects is provided. The simulation program includes a storage that stores one of an initial state, a read waiting state and a write waiting state for a channel used for data transfer between the first and second simulation objects; a receiver that receives a read request from the first simulation object to the second simulation object through the channel; a judgment unit which, upon reception of the read request, judges whether a state corresponding to the channel is the read waiting state; a transmitter which transmits data corresponding to the channel stored in a storage area to the first simulation object when judging to be the read waiting state; and a changer that changes the state to the initial state based on the data transmission.
摘要翻译：提供存储在计算机可读记录介质中以执行第一和第二仿真对象的模拟的仿真程序。模拟程序包括存储在第一和第二仿真对象之间存储用于数据传输的信道的初始状态，读等待状态和写等待状态之一; 接收器，其通过所述通道从所述第一仿真对象接收到所述第二仿真对象的读取请求; 判断单元，在接收到所述读取请求时，判断与所述通道相对应的状态是否为所述读取等待状态; 当判断为所述读取等待状态时，将与存储在存储区域中的所述通道相对应的数据发送到所述第一模拟对象的发送器; 以及基于数据传输将状态改变为初始状态的更换器。

2. 发明申请

US20100169068A1 SIMULATION PROGRAM AND SIMULATION APPARATUS 有权
标题翻译：仿真程序和仿真设备
公开(公告)号：US20100169068A1
公开(公告)日：2010-07-01
申请号：US12618137
申请日：2009-11-13
申请人： Ryo Kuya , Yasuki Nakamura , Tatsuya Yoshino
发明人： Ryo Kuya , Yasuki Nakamura , Tatsuya Yoshino
IPC分类号： G06F13/14
CPC分类号： G06F13/105 , G06F9/455
摘要： A simulation program stored in a computer readable recording medium to execute a simulation of first and second simulation objects is provided. The simulation program includes a storage that stores one of an initial state, a read waiting state and a write waiting state for a channel used for data transfer between the first and second simulation objects; a receiver that receives a read request from the first simulation object to the second simulation object through the channel; a judgment unit which, upon reception of the read request, judges whether a state corresponding to the channel is the read waiting state; a transmitter which transmits data corresponding to the channel stored in a storage area to the first simulation object when judging to be the read waiting state; and a changer that changes the state to the initial state based on the data transmission.
摘要翻译：提供存储在计算机可读记录介质中以执行第一和第二仿真对象的模拟的仿真程序。模拟程序包括存储在第一和第二仿真对象之间存储用于数据传输的信道的初始状态，读等待状态和写等待状态之一; 接收器，其通过所述通道从所述第一仿真对象接收到所述第二仿真对象的读取请求; 判断单元，在接收到所述读取请求时，判断与所述通道相对应的状态是否为所述读取等待状态; 当判断为所述读取等待状态时，将与存储在存储区域中的所述通道相对应的数据发送到所述第一模拟对象的发送器; 以及基于数据传输将状态改变为初始状态的更换器。

3. 发明授权

US08886512B2 Simulation apparatus, computer-readable recording medium, and method 有权
标题翻译：模拟装置，计算机可读记录介质和方法
公开(公告)号：US08886512B2
公开(公告)日：2014-11-11
申请号：US13196485
申请日：2011-08-02
申请人： Ryo Kuya , Yasuki Nakamura , Hiroshi Terashima , Tatsuya Yoshino , Masaharu Kimura
发明人： Ryo Kuya , Yasuki Nakamura , Hiroshi Terashima , Tatsuya Yoshino , Masaharu Kimura
IPC分类号： G06F9/44 , G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： A simulation apparatus is disclosed, including a hardware simulator and a CPU model. The hardware simulator activates one or more logical hardware models for verifying embedded software. The CPU model is one of the one or more logical hardware models which imitates a CPU which executes the embedded software, and to trigger the embedded software to operate without synchronization for each of instructions.
摘要翻译：公开了一种模拟装置，包括硬件模拟器和CPU模型。硬件模拟器激活一个或多个逻辑硬件模型以验证嵌入式软件。 CPU模型是模拟执行嵌入式软件的CPU的一个或多个逻辑硬件模型之一，并且触发嵌入式软件对每个指令进行同步操作。

4. 发明授权

US09058207B2 Simulation apparatus, method, and computer-readable recording medium 有权
标题翻译：模拟装置，方法和计算机可读记录介质
公开(公告)号：US09058207B2
公开(公告)日：2015-06-16
申请号：US13198828
申请日：2011-08-05
申请人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
发明人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4881
摘要： A simulation apparatus is disclosed, including a group switching part. The group switching part refers to a priority management table, which manages priority information of priorities to assign a CPU for multiple groups of tasks stored in a storage area, and changes the priorities of the multiple groups of tasks, when an event occurs to activate a task to be executed in verifying of software by using a simulation.
摘要翻译：公开了包括组切换部分的模拟装置。组切换部是指管理优先级管理表，其管理为存储在存储区域中的多组任务分配CPU的优先级信息，并且在发生事件时激活多个任务组的优先级，以激活通过使用仿真验证软件时执行的任务。

5. 发明申请

US20120204184A1 SIMULATION APPARATUS, METHOD, AND COMPUTER-READABLE RECORDING MEDIUM 有权
标题翻译：模拟装置，方法和计算机可读记录介质
公开(公告)号：US20120204184A1
公开(公告)日：2012-08-09
申请号：US13198828
申请日：2011-08-05
申请人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
发明人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A simulation apparatus is disclosed, including a group switching part. The group switching part refers to a priority management table, which manages priority information of priorities to assign a CPU for multiple groups of tasks stored in a storage area, and changes the priorities of the multiple groups of tasks, when an event occurs to activate a task to be executed in verifying of software by using a simulation.
摘要翻译：公开了包括组切换部分的模拟装置。组切换部是指管理优先级管理表，其管理为存储在存储区域中的多组任务分配CPU的优先级信息，并且在发生事件时激活多个任务组的优先级，以激活通过使用仿真验证软件时执行的任务。

6. 发明申请

US20120089386A1 SIMULATION APPARATUS, COMPUTER-READABLE RECORDING MEDIUM, AND METHOD 有权
标题翻译：模拟装置，计算机可读记录介质和方法
公开(公告)号：US20120089386A1
公开(公告)日：2012-04-12
申请号：US13196485
申请日：2011-08-02
申请人： Ryo KUYA , Yasuki Nakamura , Hiroshi Terashima , Tatsuya Yoshino , Masaharu Kimura
发明人： Ryo KUYA , Yasuki Nakamura , Hiroshi Terashima , Tatsuya Yoshino , Masaharu Kimura
IPC分类号： G06F9/44
CPC分类号： G06F17/5022 , G06F2217/86
摘要： A simulation apparatus is disclosed, including a hardware simulator and a CPU model. The hardware simulator activates one or more logical hardware models for verifying embedded software. The CPU model is one of the one or more logical hardware models which imitates a CPU which executes the embedded software, and to trigger the embedded software to operate without synchronization for each of instructions.
摘要翻译：公开了一种模拟装置，包括硬件模拟器和CPU模型。硬件模拟器激活一个或多个逻辑硬件模型以验证嵌入式软件。 CPU模型是模拟执行嵌入式软件的CPU的一个或多个逻辑硬件模型之一，并且触发嵌入式软件对每个指令进行同步操作。

7. 发明授权

US07581090B2 Interrupt control apparatus and method 有权
标题翻译：中断控制装置及方法
公开(公告)号：US07581090B2
公开(公告)日：2009-08-25
申请号：US10692800
申请日：2003-10-27
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F13/24
摘要： When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
摘要翻译：当正常中断发生时，在正常中断之前的处理器操作的数据被保存在正常的返回地址寄存器（452），正常的先前状态寄存器（453）和正常因子寄存器（454）中。当发生中断中断时，中断中断前的处理器操作数据保存在另一个中断返回地址寄存器（455）中。因此，即使在正常中断的中断禁止期间，中断也可能发生。此外，当发生中断中断时，中断中断状态被设置在标志寄存器（456）中。通过参考标志寄存器（456）执行中断返回指令，可以准确地恢复中断中断前或正常中断前的操作数据。

8. 发明申请

US20100070739A1 Multiprocessor system and control method thereof 有权
标题翻译：多处理器系统及其控制方法
公开(公告)号：US20100070739A1
公开(公告)日：2010-03-18
申请号：US12585620
申请日：2009-09-18
申请人： Yasuki Nakamura , Takahisa SUZUKI , Makiko ITO , Hideo MIYAKE
发明人： Yasuki Nakamura , Takahisa SUZUKI , Makiko ITO , Hideo MIYAKE
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/54
摘要： A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information.
摘要翻译：根据实施例的多处理器系统包括多个处理器，执行控制单元，用于控制多个处理器的处理和多个处理器之间的数据传送; 以及内部数据存储单元，用于存储指示数据传送状态的数据相关信息。如果在先前的数据传送被注册执行之后处理器的处理的控制流程是固定的，并且需要与之前的数据传送相同的目的地的另一数据传送，则执行控制单元基于数据依赖信息来取消先前的数据传送。

9. 发明授权

US06868472B1 Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory 失效
标题翻译：控制和寻址作为随机地址存储器以增加对主存储器的访问速度的高速缓冲存储器的方法
公开(公告)号：US06868472B1
公开(公告)日：2005-03-15
申请号：US09671117
申请日：2000-09-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515
摘要： In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.
摘要翻译：在本发明的高速缓冲存储器控制方法和计算机中，高速缓存存储器连接到主存储器并被分成多个高速缓存块，并且锁定/解锁信号被提供给高速缓冲存储器以设置替换抑制禁止将至少一个高速缓存块替换为主存储器的至少一个缓存块的状态，或者重置至少一个高速缓冲存储器时钟的替换禁止状态，使得更换高速缓存中的至少一个阻塞到主内存是允许的。通过使用高速缓冲存储器的其余高速缓冲存储器（除了至少一个高速缓存块之外）来执行读取或写入主存储器，使得当通过锁定/解锁信号设置替换禁止状态时，在主存储器的读取或写入期间禁止将至少一个缓存块替换到主存储器。

10. 发明申请

US20080215859A1 Computer with high-speed context switching 审中-公开
标题翻译：具有高速上下文切换的计算机
公开(公告)号：US20080215859A1
公开(公告)日：2008-09-04
申请号：US12073042
申请日：2008-02-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
IPC分类号： G06F9/312 , G06F9/302
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/461 , G06F9/5016 , G06F2207/5353 , Y02D10/22
摘要： A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.
摘要翻译：以时分方式执行多个程序的并行处理的计算机包括划分为多个区域的硬件资源，记录识别第一程序的识别信息的撤离单元，以及排除存储在所述多个区域的区域中的信息如果该区域是执行第二程序所必需的并被用于执行第一程序的区域，以及恢复单元，其在第二程序停止时基于识别信息将该撤离信息恢复到该区域，或者结束。

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