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1. 发明申请

US20100070739A1 Multiprocessor system and control method thereof 有权
标题翻译：多处理器系统及其控制方法
公开(公告)号：US20100070739A1
公开(公告)日：2010-03-18
申请号：US12585620
申请日：2009-09-18
申请人： Yasuki Nakamura , Takahisa SUZUKI , Makiko ITO , Hideo MIYAKE
发明人： Yasuki Nakamura , Takahisa SUZUKI , Makiko ITO , Hideo MIYAKE
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/54
摘要： A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information.
摘要翻译：根据实施例的多处理器系统包括多个处理器，执行控制单元，用于控制多个处理器的处理和多个处理器之间的数据传送; 以及内部数据存储单元，用于存储指示数据传送状态的数据相关信息。如果在先前的数据传送被注册执行之后处理器的处理的控制流程是固定的，并且需要与之前的数据传送相同的目的地的另一数据传送，则执行控制单元基于数据依赖信息来取消先前的数据传送。

2. 发明申请

US20090019259A1 MULTIPROCESSING METHOD AND MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：多处理方法和多处理器系统
公开(公告)号：US20090019259A1
公开(公告)日：2009-01-15
申请号：US12235209
申请日：2008-09-22
申请人： Takahisa SUZUKI , Makiko Ito , Hideo Miyake
发明人： Takahisa SUZUKI , Makiko Ito , Hideo Miyake
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/5038
摘要： A multiprocessing method and a multiprocessor system capable of reducing time lost due to sequential waiting when procedures (program units) having dependencies are executed in which an order of execution of a plurality of program units in a sequential execution program and dependencies of the plurality of program units are registered, the execution states of the plurality of program units are managed based on the registered dependencies, executable program units are determined, and are assigned to server processors sequentially and executed are disclosed.
摘要翻译：一种多处理方法和多处理器系统，其能够在顺序执行程序中执行多个程序单元的执行顺序和多个程序的依赖性时执行具有依赖关系的程序（程序单元）时由于顺序等待而减少时间损失注册单元，基于注册的依赖关系管理多个程序单元的执行状态，确定可执行程序单元，并且依次分配给服务器处理器并执行。

3. 发明申请

US20110078378A1 METHOD FOR GENERATING PROGRAM AND METHOD FOR OPERATING SYSTEM 失效
标题翻译：用于生成程序的方法和操作系统的方法
公开(公告)号：US20110078378A1
公开(公告)日：2011-03-31
申请号：US12888614
申请日：2010-09-23
申请人： Takahisa SUZUKI , Hiromasa YAMAUCHI , Hideo MIYAKE , Makiko ITO
发明人： Takahisa SUZUKI , Hiromasa YAMAUCHI , Hideo MIYAKE , Makiko ITO
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/445 , G06F9/44557
摘要： An information processing apparatus sequentially selects a function whose execution frequency is high as a selected function that is to be stored in an internal memory, in a source program having a hierarchy structure. The information processing apparatus allocates the selected function to a memory area of the internal memory, allocates a function that is not the selected function and is called from the selected function to an area close to the memory area of the internal memory, and generates an internal load module. The information processing apparatus allocates a remaining function to an external memory coupled to a processor and generates an external load module. Then, a program executed by the processor having the internal memory is generated. By allocating the function with a high execution frequency to the internal memory, it is possible to execute the program at high speed, which may improve performance of a system.
摘要翻译：在具有层次结构的源程序中，信息处理装置顺序选择执行频率高的功能作为要存储在内部存储器中的选择功能。信息处理装置将所选择的功能分配给内部存储器的存储区域，分配不是所选功能的功能，并且从所选择的功能调用到靠近内部存储器的存储区域的区域，并且生成内部加载模块。信息处理装置将剩余的功能分配给耦合到处理器的外部存储器，并生成外部负载模块。然后，生成由具有内部存储器的处理器执行的程序。通过将高执行频率的功能分配给内部存储器，可以高速执行程序，这可以提高系统的性能。

4. 发明申请

US20100107174A1 SCHEDULER, PROCESSOR SYSTEM, AND PROGRAM GENERATION METHOD 审中-公开
标题翻译：调度器，处理器系统和程序生成方法
公开(公告)号：US20100107174A1
公开(公告)日：2010-04-29
申请号：US12606837
申请日：2009-10-27
申请人： Takahisa SUZUKI , Makiko Ito
发明人： Takahisa SUZUKI , Makiko Ito
IPC分类号： G06F9/50
CPC分类号： G06F9/5033
摘要： A scheduler for conducting scheduling for a processor system including a plurality of processor cores and a plurality of memories respectively corresponding to the plurality of processor cores includes: a scheduling section that allocates one of the plurality of processor cores to one of a plurality of process requests corresponding to a process group based on rule information; and a rule changing section that, when a first processor core is allocated to a first process of the process group, changes the rule information and allocates the first processor core to a subsequent process of the process group, and that restores the rule information when a second processor core is allocated to a final process of the process group.
摘要翻译：用于对包括分别对应于所述多个处理器核心的多个处理器核和多个存储器的处理器系统进行调度的调度器包括：调度部分，其将所述多个处理器核中的一个分配到多个处理请求之一对应于基于规则信息的进程组; 以及规则变更部，其中当第一处理器核被分配给所述进程组的第一进程时，改变所述规则信息并将所述第一处理器核分配给所述进程组的后续进程，并且当第二处理器核心被分配给进程组的最后进程。

5. 发明申请

US20080288967A1 PROCEDURE CALLING METHOD, PROCEDURE CALLING PROGRAM, AND COMPUTER PRODUCT 审中-公开
标题翻译：程序呼叫方法，程序呼叫程序和计算机产品
公开(公告)号：US20080288967A1
公开(公告)日：2008-11-20
申请号：US12184000
申请日：2008-07-31
申请人： Takahisa SUZUKI , Hideo Miyake
发明人： Takahisa SUZUKI , Hideo Miyake
IPC分类号： G06F9/46
CPC分类号： G06F9/547 , H04L67/40
摘要： In a shared-memory multiprocessor having plural processors that share a shared memory, each have an address space that is respectively independent in the shared memory and are configured to be capable of inter-processor communication using a bus, a first processor makes a procedure call to a second processor by specifying an address in the address space of the second processor. In response to the procedure call, by initiating and executing the procedure located at the address specified by the first processor, the second processor initiates the procedure at a high speed.
摘要翻译：在具有共享共享存储器的多个处理器的共享存储器多处理器中，每个存储器具有分别独立于共享存储器中的地址空间，并且被配置为能够使用总线进行处理器间通信，第一处理器进行过程调用通过指定第二处理器的地址空间中的地址到第二处理器。响应于过程调用，通过启动和执行位于由第一处理器指定的地址的过程，第二处理器以高速启动过程。

6. 发明申请

US20100313041A1 POWER MANAGEMENT CIRCUIT, POWER MANAGEMENT METHOD AND POWER MANAGEMENT PROGRAM 失效
标题翻译：电源管理电路，电源管理方法和电源管理程序
公开(公告)号：US20100313041A1
公开(公告)日：2010-12-09
申请号：US12795402
申请日：2010-06-07
申请人： Takahisa SUZUKI , Hideo MIYAKE
发明人： Takahisa SUZUKI , Hideo MIYAKE
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A power management circuit has a resource management unit which performs a use management of a functional block in an integrated circuit, and a power management unit which transmits a power control request to a power control device which controls power of the functional block for each domain. The power control request designates the domain and the power control content for the domain. The power management unit executes a use prohibition process prohibiting the use of the functional block belonging to the domain, by using the resource management unit, before transmitting the power control request to the power control device, in accordance with a type of the functional block belonging to the domain and the power control content.
摘要翻译：功率管理电路具有执行集成电路中的功能块的使用管理的资源管理单元和向功率控制装置发送功率控制请求的功率管理单元，该功率控制装置控制各个功能块的功率。功率控制请求指定域的域和功率控制内容。功率管理单元根据所属功能块的类型，在向功率控制装置发送功率控制请求之前，通过使用资源管理单元，执行禁止使用属于该域的功能块的使用禁止处理到域和电源控制内容。

7. 发明申请

US20110089431A1 COMPOUND SINGLE CRYSTAL AND METHOD FOR PRODUCING THE SAME 审中-公开
标题翻译：化合物单晶及其制造方法
公开(公告)号：US20110089431A1
公开(公告)日：2011-04-21
申请号：US12905355
申请日：2010-10-15
申请人： Kuniaki YAGI , Takahisa SUZUKI , Yasutaka YANAGISAWA , Masao HIROSE , Noriko SATO , Junya KOIZUMI , Hiroyuki NAGASAWA
发明人： Kuniaki YAGI , Takahisa SUZUKI , Yasutaka YANAGISAWA , Masao HIROSE , Noriko SATO , Junya KOIZUMI , Hiroyuki NAGASAWA
IPC分类号： H01L29/24 , C30B25/18 , C30B23/02 , C30B19/12
CPC分类号： C30B29/06 , C30B25/02 , C30B25/18 , C30B29/36
摘要： A method for producing a compound single crystal includes a process (I) of growing the compound single crystal while causing an anti-phase boundary and a stacking fault to equivalently occur in a direction parallel to the surface, the stacking fault being attributable to the elements A and B; a process (II) of merging and annihilating the stacking fault, attributable to the element A, and the anti-phase boundary, which occurs in the process (I); a process (III) of vanishing the stacking fault attributable to the element B, which occurs in the process (I); and a process (IV) of completely merging and annihilating the anti-phase boundary. The process (IV) is carried out simultaneously with the processes (II) and (III) or after the processes (II) and (III).
摘要翻译：一种化合物单晶的制造方法包括在平行于表面的<110>方向等价地发生复合单晶同时引起反相边界和堆垛层错的方法（I），堆垛层错归因于元素A和B; 合并和湮没归属于元素A的堆垛层错的过程（II）和在过程（I）中发生的反相边界）。在过程（I）中发生的消除归因于元件B的堆垛层错的过程（III）; 以及完全合并消除反相边界的方法（Ⅳ）。方法（IV）与方法（II）和（III）或方法（II）和（III）同时进行。

8. 发明申请

US20110277574A1 CONNECTING APPARATUS OF A VEHICLE SEAT 审中-公开
标题翻译：连接车辆座椅的装置
公开(公告)号：US20110277574A1
公开(公告)日：2011-11-17
申请号：US13108148
申请日：2011-05-16
申请人： Atsutaka MITSUHASHI , Takahisa SUZUKI
发明人： Atsutaka MITSUHASHI , Takahisa SUZUKI
IPC分类号： F16H57/10
CPC分类号： B60N2/2252 , B60N2/2254 , Y10T74/19637
摘要： A connecting apparatus of a vehicle seat includes a member with internal teeth; a member with external teeth that is assembled to the member with internal teeth so as to rotate relative to the member with internal teeth while changing a meshing position; a pair of wedge members that are arranged in a gap between the members, and that prevent the members from relative rotation by being urged in a circumferential direction of the connecting members, while sliding against the connecting members, so as to become jammed between the connecting members; and an operating shaft that moves the wedge members in a direction against the urging force, and rotates the gear with external teeth with respect to the gear with internal teeth. A resin composition in which polyethylene has been added to a binder resin is coated onto sliding surfaces of the wedge members.
摘要翻译：车辆座椅的连接装置包括具有内齿的构件; 具有外齿的构件，其组装到具有内齿的构件，以便在改变啮合位置的同时相对于具有内齿的构件旋转; 一对楔形构件，其布置在构件之间的间隙中，并且通过在连接构件的圆周方向上被推压而防止构件相对旋转，同时相对于连接构件滑动，从而在连接会员以及操作轴，其使楔形构件沿着抵抗推力的方向移动，并且使齿轮与外齿相对于具有内齿的齿轮旋转。将其中已经加入聚乙烯的树脂组合物涂覆到楔形构件的滑动表面上。

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