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1. 发明申请

US20080215859A1 Computer with high-speed context switching 审中-公开
标题翻译：具有高速上下文切换的计算机
公开(公告)号：US20080215859A1
公开(公告)日：2008-09-04
申请号：US12073042
申请日：2008-02-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
IPC分类号： G06F9/312 , G06F9/302
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/461 , G06F9/5016 , G06F2207/5353 , Y02D10/22
摘要： A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.
摘要翻译：以时分方式执行多个程序的并行处理的计算机包括划分为多个区域的硬件资源，记录识别第一程序的识别信息的撤离单元，以及排除存储在所述多个区域的区域中的信息如果该区域是执行第二程序所必需的并被用于执行第一程序的区域，以及恢复单元，其在第二程序停止时基于识别信息将该撤离信息恢复到该区域，或者结束。

2. 发明授权

US07401204B1 Parallel Processor efficiently executing variable instruction word 有权
标题翻译：并行处理器有效执行可变指令字
公开(公告)号：US07401204B1
公开(公告)日：2008-07-15
申请号：US09654527
申请日：2000-09-01
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
IPC分类号： G06F15/00
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.
摘要翻译：并行处理器对包含在由指令定界信息定界的多个指令字中的每个指令字中的一个或多个基本指令执行高效的并行处理。处理器包括：多个指令执行单元，并行地执行根据相应的所提供的基本指令的处理; 指令读取单元根据指令定界信息逐个取出指令字; 以及指令发布单元，其识别并且根据其选择包含在由指令获取单元获取的每个指令字中的每个基本指令给相应的指令执行单元以执行基本指令。

3. 发明授权

US07134004B1 Processing device for buffering sequential and target sequences and target address information for multiple branch instructions 失效
标题翻译：用于缓冲顺序和目标序列的处理设备以及多个分支指令的目标地址信息
公开(公告)号：US07134004B1
公开(公告)日：2006-11-07
申请号：US09666853
申请日：2000-09-20
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
摘要翻译：信息处理装置通过流水线处理从指令存储部分读取，缓冲，解码和执行指令，包括：向指令存储部分分配读取地址的指令读取请求部分，包括多个指令缓冲器的指令缓冲部分，缓冲从指令存储部分读取的指令序列; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行。分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息。

4. 发明申请

US20060224870A1 Information processing device 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20060224870A1
公开(公告)日：2006-10-05
申请号：US11444221
申请日：2006-05-31
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.
摘要翻译：本发明的定义在于，通过流水线处理从指令存储部分读取，缓冲，解码和执行指令的信息处理设备包括：指令读取请求部分，其向指令存储部分分配读取地址; 指令缓冲部分，包括缓冲从指令存储部分读取的指令序列的多个指令缓冲器; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行; 分支指令检测部分，其检测从指令存储部分读取的指令序列中的分支指令; 以及分支目标地址信息缓冲部分，包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息; 其中，当分支指令检测部分已经检测到分支指令时，分支指令的分支目标地址信息被存储在多个分支目标地址信息缓冲器中的一个中，或分支指令的分支目标指令序列被存储除了存储在分支目标地址信息缓冲器之外，还包括在多个指令缓冲器之一中。

5. 发明申请

US20060143416A1 Multiprocessor system with high-speed exclusive control 有权
标题翻译：具有高速独占控制的多处理器系统
公开(公告)号：US20060143416A1
公开(公告)日：2006-06-29
申请号：US11113056
申请日：2005-04-25
申请人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
发明人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
IPC分类号： G06F12/14
CPC分类号： G06F9/526
摘要： A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.
摘要翻译：多处理器系统包括多个处理器，耦合到多个处理器的共享总线，耦合到共享总线并被多个处理器共享的资源，以及耦合到多个处理器的排他控制单元，并且被配置为包括指示关于资源的独占使用的锁定/解锁状态的锁定标志，其中处理器包括耦合到排他控制单元的专用寄存器接口，并且被配置为通过专用寄存器访问专用寄存器访问锁定标志接口。

6. 发明授权

US07546445B2 Information processor having delayed branch function with storing delay slot information together with branch history information 有权
标题翻译：具有延迟分支功能的信息处理器，具有存储延迟时隙信息以及分支历史信息
公开(公告)号：US07546445B2
公开(公告)日：2009-06-09
申请号：US10438986
申请日：2003-05-16
申请人： Shinichiro Tago , Tomohiro Yamana , Yoshimasa Takebe
发明人： Shinichiro Tago , Tomohiro Yamana , Yoshimasa Takebe
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3842 , G06F9/3853
摘要： In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay slot instructions are stored in a branch target buffer 241. A branch prediction circuit 23 outputs hit information H/M as to whether or not an input address Ao is coincident with the branch instruction address, the valid bit which is also a branch prediction bit, the information POS, and the branch target address Apb. When a prediction error signal ERR is inactive, the address selection circuit 22 selectively outputs the output of an incrementer 21 and the branch target address Apb, based on the hit information H/M, the delay slot information POS, and the valid bit V.
摘要翻译：对应于分支指令的地址，分支目标地址Apb，作为分支历史信息的有效位V和延迟时隙指令的最后位置的延迟时隙信息POS被存储在分支目标缓冲器241中。分支预测电路23输出与输入地址Ao是否与分支指令地址一致的命中信息H / M，也是分支预测位的有效位，信息POS和分支目标地址Apb。当预测误差信号ERR不活动时，地址选择电路22基于命中信息H / M，延迟时隙信息POS和有效位V选择性地输出增量器21和分支目标地址Apb的输出。

7. 发明授权

US07409506B2 Multiprocessor system with high-speed exclusive control 有权
标题翻译：具有高速独占控制的多处理器系统
公开(公告)号：US07409506B2
公开(公告)日：2008-08-05
申请号：US11113056
申请日：2005-04-25
申请人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
发明人： Teruhiko Kamigata , Shinichiro Tago , Atsushi Ike , Yoshimasa Takebe
IPC分类号： G06F13/18 , G06F13/16
CPC分类号： G06F9/526
摘要： A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.
摘要翻译：多处理器系统包括多个处理器，耦合到多个处理器的共享总线，耦合到共享总线并被多个处理器共享的资源，以及耦合到多个处理器的排他控制单元，并且被配置为包括指示关于资源的独占使用的锁定/解锁状态的锁定标志，其中处理器包括耦合到排他控制单元的专用寄存器接口，并且被配置为通过专用寄存器访问专用寄存器访问锁定标志接口。

8. 发明授权

US07055023B2 Apparatus and method for branch prediction where data for predictions is selected from a count in a branch history table or a bias in a branch target buffer 有权
标题翻译：用于分支预测的装置和方法，其中从分支历史表中的计数或分支目标缓冲器中的偏差中选择用于预测的数据
公开(公告)号：US07055023B2
公开(公告)日：2006-05-30
申请号：US10091147
申请日：2002-03-06
申请人： Shinichiro Tago , Tomohiro Yamana , Yoshimasa Takebe
发明人： Shinichiro Tago , Tomohiro Yamana , Yoshimasa Takebe
IPC分类号： G06F9/32
CPC分类号： G06F9/3806 , G06F9/3848
摘要： An apparatus for branch prediction includes a history register which stores therein history of previous branch instructions, an index generation circuit which generates a first index from an instruction address and the history stored in the history register, a history table which stores therein a portion of the instruction address as a tag and a first value indicative of likelihood of branching in association with the first index, a branch destination buffer which stores therein a branch destination address or predicted branch destination address of an instruction indicated by the instruction address and a second value indicative of likelihood of branching in association with a second index that is at least a portion of the instruction address, and a selection unit which makes a branch prediction by selecting one of the first value and the second value.
摘要翻译：一种用于分支预测的装置包括：历史寄存器，其存储先前分支指令的历史，从指令地址生成第一索引的索引生成电路和存储在历史寄存器中的历史;历史表，其中存储有指示地址作为标签，以及指示与第一索引相关联的分支的可能性的第一值;分支目的地缓冲器，其中存储由指令地址指示的指令的分支目的地地址或预测分支目的地地址，以及第二值指示与作为指令地址的至少一部分的第二索引相关联的分支的可能性，以及通过选择第一值和第二值中的一个进行分支预测的选择单元。

9. 发明申请

US20090172296A1 Cache Memory System and Cache Memory Control Method 审中-公开
标题翻译：缓存内存系统和缓存内存控制方法
公开(公告)号：US20090172296A1
公开(公告)日：2009-07-02
申请号：US12343251
申请日：2008-12-23
申请人： Masayuki TSUJI , Yoshimasa Takebe , Akira Nodomi
发明人： Masayuki TSUJI , Yoshimasa Takebe , Akira Nodomi
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F2212/1044
摘要： A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area of the address to the cache memory in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data, and a second operation mode in response to a generation of a cache miss due to the access to the address and storing the write data to the cache memory without copying data of the address of the main memory unit to the allocated area on the cache memory.
摘要翻译：一种高速缓冲存储器系统，包括连接到处理单元的处理单元和高速缓存存储器，其中当执行将写入数据存储到特定地址的存储指令时，高速缓冲存储器系统选择性地执行以下操作中的一种：第一操作模式响应于由于访问地址而产生高速缓存未命中而将地址的区域分配给高速缓冲存储器，将主存储器单元的地址的数据复制到高速缓冲存储器，然后在缓存上重写复制的数据存储器，以及响应于由于访问地址而产生高速缓存未命中的第二操作模式，并且将写入数据存储到高速缓冲存储器，而不将主存储器单元的地址的数据复制到所分配的缓存中的区域。

10. 发明申请

US20070028071A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20070028071A1
公开(公告)日：2007-02-01
申请号：US11271913
申请日：2005-11-14
申请人： Akira Nodomi , Yoshimasa Takebe
发明人： Akira Nodomi , Yoshimasa Takebe
IPC分类号： G06F12/00
CPC分类号： G06F12/0802
摘要： A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.
摘要翻译：一种可以处理各种传输源设备和传输目的地设备而不修改硬件配置的存储设备。存储装置用于发送和接收数据，并且包括数据缓冲器，用于存储从数据传输源输出的数据，并将数据输出到作为数据输出目的地的数据传输目的地; 发送源地址转换器，用于当数据发送源是被动地输出数据的设备时，对从数据发送源输出的数据进行配置处理; 以及发送目的地地址转换器，用于当数据发送目的地是被动地输入数据的设备时，对要输入到数据发送目的地的数据进行配置处理。

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