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1. 发明授权

US06603321B2 Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring 失效
标题翻译：用于加速确定半导体布线的电迁移特性的方法和装置
公开(公告)号：US06603321B2
公开(公告)日：2003-08-05
申请号：US09999719
申请日：2001-10-26
申请人： Ronald G. Filippi, Jr. , Alvin W. Strong , Timothy D. Sullivan , Deborah Tibel , Michael Ruprecht , Carole Graas
发明人： Ronald G. Filippi, Jr. , Alvin W. Strong , Timothy D. Sullivan , Deborah Tibel , Michael Ruprecht , Carole Graas
IPC分类号： G01R3126
CPC分类号： H01L22/34 , G01R31/2858 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type. Then, at least one parameter value for is determined for the first individual test structure, which parameter value is used to predict a lifetime projection for the wiring structure in the integrated circuit device.
摘要翻译：公开了一种用于确定集成电路器件中的布线结构的电迁移特性的方法。在本发明的示例性实施例中，该方法包括配置用于集成电路器件的定义的测试结构类型。所确定的测试结构类型还包括主要布置在半导体衬底的主平面中的第一布线和连接到第一布线的第二布线。布线的第二线设置在基本上平行于主平面的二次平面中，其中第一和第二布线通过它们之间的通孔结构连接。确定第一线路和通孔结构的电阻的热系数，并且在限定的测试结构类型的第一单独测试结构中引入晶片级应力条件。然后，对于第一单独测试结构确定至少一个参数值，哪个参数值用于预测集成电路器件中的布线结构的寿命投影。

2. 发明授权

US08018017B2 Thermo-mechanical cleavable structure 有权
标题翻译：热机械可切割结构
公开(公告)号：US08018017B2
公开(公告)日：2011-09-13
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
发明人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
IPC分类号： H01L31/058
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

3. 发明授权

US07096450B2 Enhancement of performance of a conductive wire in a multilayered substrate 失效
公开(公告)号：US07096450B2
公开(公告)日：2006-08-22
申请号：US10604165
申请日：2003-06-28
申请人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
发明人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

4. 发明授权

US07512506B2 IC chip stress testing 失效
标题翻译： IC芯片压力测试
公开(公告)号：US07512506B2
公开(公告)日：2009-03-31
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流Is; 并且在施加恒定电流Is的同时对线进行应力测试，使得恒定电流Is不会由于电迁移开始时的电阻变化而改变。

5. 发明授权

US07511378B2 Enhancement of performance of a conductive wire in a multilayered substrate 失效
标题翻译：提高多层基板中的导线的性能
公开(公告)号：US07511378B2
公开(公告)日：2009-03-31
申请号：US11442911
申请日：2006-05-30
申请人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
发明人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
IPC分类号： H01L23/48
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.
摘要翻译：具有布线的电子结构以及用于限制布线中的温度梯度的结构设计的相关方法。该电子结构包括具有包括不物理接触的第一和第二线的层的衬底。由于焦耳加热相对于第一和第二导线中的电流密度，第一和第二导线适于处于升高的温度。第一导线通过存在于层之外的导电和导热结构电耦合到第二导线。第二导线的宽度被调整为将第一导线中的温度梯度限制在低于预定足够小的阈值，以便基本上减轻第一线中的电迁移的不利影响。

6. 发明申请

US20080297188A1 IC CHIP STRESS TESTING 失效
标题翻译： IC芯片应力测试
公开(公告)号：US20080297188A1
公开(公告)日：2008-12-04
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

7. 发明授权

US09035459B2 Structures for improving current carrying capability of interconnects and methods of fabricating the same 有权
标题翻译：用于改善互连的载流能力的结构及其制造方法
公开(公告)号：US09035459B2
公开(公告)日：2015-05-19
申请号：US12421723
申请日：2009-04-10
申请人： Charles L. Arvin , Raschid J. Bezama , Harry D. Cox , Timothy H. Daubenspeck , Krystyna W. Semkow , Timothy D. Sullivan
发明人： Charles L. Arvin , Raschid J. Bezama , Harry D. Cox , Timothy H. Daubenspeck , Krystyna W. Semkow , Timothy D. Sullivan
IPC分类号： C23C14/24 , H01L23/00 , C25D5/02 , C25D5/14 , C25D5/48
CPC分类号： H01L24/05 , C25D5/02 , C25D5/14 , C25D5/48 , H01L24/11 , H01L2224/0401 , H01L2224/05075 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2924/01322 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/00 , H01L2924/00014 , H01L2924/01074 , H01L2924/013 , H01L2924/01027
摘要： Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.
摘要翻译：提供互连结构及其制造方法。互连结构提供用于改善载流能力（例如，电流扩展）的高可靠性铜互连结构。该结构包括在沟槽中形成的凸块下金属。凸起下冶金至少包括：粘合层; 电镀阻挡层; 以及设置在粘合层和镀层阻挡层之间的镀覆导电金属层。该结构还包括形成在凸块下金属上的焊料凸块。

8. 发明授权

US08652922B2 Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture 有权
标题翻译：紧凑的热控薄膜电阻器，利用基板触点和制造方法
公开(公告)号：US08652922B2
公开(公告)日：2014-02-18
申请号：US13008459
申请日：2011-01-18
申请人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
发明人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L27/0207 , H01L27/1203
摘要： A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.
摘要翻译：形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并在电阻器中形成沟槽并进入衬底。该方法还包括在沟槽的侧壁上形成衬垫，并在沟槽和衬垫上形成包括高导热性材料的芯。

9. 发明授权

US08647909B2 Array of alpha particle sensors 失效
标题翻译： α粒子传感器阵列
公开(公告)号：US08647909B2
公开(公告)日：2014-02-11
申请号：US13357728
申请日：2012-01-25
申请人： Ethan H. Cannon , Michael J. Hauser , Timothy D. Sullivan
发明人： Ethan H. Cannon , Michael J. Hauser , Timothy D. Sullivan
IPC分类号： H01L21/00
CPC分类号： H01L31/115 , H01L23/552 , H01L23/556 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).
摘要翻译：辐射传感器或检测器阵列集成在三维半导体IC内。传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。

10. 发明申请

US20130299989A1 CHIP CONNECTION STRUCTURE AND METHOD OF FORMING 审中-公开
公开(公告)号：US20130299989A1
公开(公告)日：2013-11-14
申请号：US13468750
申请日：2012-05-10
申请人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L24/11 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03452 , H01L2224/0346 , H01L2224/0348 , H01L2224/03912 , H01L2224/0401 , H01L2224/05026 , H01L2224/05147 , H01L2224/05571 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2224/11005 , H01L2224/11452 , H01L2224/1146 , H01L2224/11472 , H01L2224/11903 , H01L2224/11906 , H01L2224/13 , H01L2224/13006 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer.

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