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1. 发明授权

US07512506B2 IC chip stress testing 失效
标题翻译： IC芯片压力测试
公开(公告)号：US07512506B2
公开(公告)日：2009-03-31
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流Is; 并且在施加恒定电流Is的同时对线进行应力测试，使得恒定电流Is不会由于电迁移开始时的电阻变化而改变。

2. 发明申请

US20080297188A1 IC CHIP STRESS TESTING 失效
标题翻译： IC芯片应力测试
公开(公告)号：US20080297188A1
公开(公告)日：2008-12-04
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

3. 发明授权

US07096450B2 Enhancement of performance of a conductive wire in a multilayered substrate 失效
公开(公告)号：US07096450B2
公开(公告)日：2006-08-22
申请号：US10604165
申请日：2003-06-28
申请人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
发明人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

4. 发明授权

US07511378B2 Enhancement of performance of a conductive wire in a multilayered substrate 失效
标题翻译：提高多层基板中的导线的性能
公开(公告)号：US07511378B2
公开(公告)日：2009-03-31
申请号：US11442911
申请日：2006-05-30
申请人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
发明人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
IPC分类号： H01L23/48
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.
摘要翻译：具有布线的电子结构以及用于限制布线中的温度梯度的结构设计的相关方法。该电子结构包括具有包括不物理接触的第一和第二线的层的衬底。由于焦耳加热相对于第一和第二导线中的电流密度，第一和第二导线适于处于升高的温度。第一导线通过存在于层之外的导电和导热结构电耦合到第二导线。第二导线的宽度被调整为将第一导线中的温度梯度限制在低于预定足够小的阈值，以便基本上减轻第一线中的电迁移的不利影响。

5. 发明授权

US08018017B2 Thermo-mechanical cleavable structure 有权
标题翻译：热机械可切割结构
公开(公告)号：US08018017B2
公开(公告)日：2011-09-13
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
发明人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
IPC分类号： H01L31/058
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

6. 发明授权

US08592947B2 Thermally controlled refractory metal resistor 有权
$Thermally controlled refractory metal resistor$
标题翻译：耐热耐火金属电阻
公开(公告)号：US08592947B2
公开(公告)日：2013-11-26
申请号：US12962722
申请日：2010-12-08
申请人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
发明人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L23/36
CPC分类号： H01L28/20 , H01L23/3677 , H01L23/5228 , H01L27/0211 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
摘要翻译：制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。一个电阻器被包含在最上层的上方的层中。垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

7. 发明申请

US20120146186A1 THERMALLY CONTROLLED REFRACTORY METAL RESISTOR 有权
标题翻译：热控制的金属电阻器
公开(公告)号：US20120146186A1
公开(公告)日：2012-06-14
申请号：US12962722
申请日：2010-12-08
申请人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
发明人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/20 , H01L23/3677 , H01L23/5228 , H01L27/0211 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
摘要翻译：制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。一个电阻器被包含在最上层的上方的层中。垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

8. 发明授权

US06603321B2 Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring 失效
标题翻译：用于加速确定半导体布线的电迁移特性的方法和装置
公开(公告)号：US06603321B2
公开(公告)日：2003-08-05
申请号：US09999719
申请日：2001-10-26
申请人： Ronald G. Filippi, Jr. , Alvin W. Strong , Timothy D. Sullivan , Deborah Tibel , Michael Ruprecht , Carole Graas
发明人： Ronald G. Filippi, Jr. , Alvin W. Strong , Timothy D. Sullivan , Deborah Tibel , Michael Ruprecht , Carole Graas
IPC分类号： G01R3126
CPC分类号： H01L22/34 , G01R31/2858 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type. Then, at least one parameter value for is determined for the first individual test structure, which parameter value is used to predict a lifetime projection for the wiring structure in the integrated circuit device.
摘要翻译：公开了一种用于确定集成电路器件中的布线结构的电迁移特性的方法。在本发明的示例性实施例中，该方法包括配置用于集成电路器件的定义的测试结构类型。所确定的测试结构类型还包括主要布置在半导体衬底的主平面中的第一布线和连接到第一布线的第二布线。布线的第二线设置在基本上平行于主平面的二次平面中，其中第一和第二布线通过它们之间的通孔结构连接。确定第一线路和通孔结构的电阻的热系数，并且在限定的测试结构类型的第一单独测试结构中引入晶片级应力条件。然后，对于第一单独测试结构确定至少一个参数值，哪个参数值用于预测集成电路器件中的布线结构的寿命投影。

9. 发明授权

US07692439B2 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US07692439B2
公开(公告)日：2010-04-06
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

10. 发明授权

US07890893B2 Design structure for semiconductor on-chip repair scheme for negative bias temperature instability 有权
标题翻译：用于负偏压温度不稳定性的半导体片上修复方案的设计结构
公开(公告)号：US07890893B2
公开(公告)日：2011-02-15
申请号：US12050990
申请日：2008-03-19
申请人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
发明人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L23/345 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.
摘要翻译：公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。修理方案在每个设备上使用加热元件。加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

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