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1. 发明授权

US08765595B2 Thick on-chip high-performance wiring structures 有权
标题翻译：厚片上高性能布线结构
公开(公告)号：US08765595B2
公开(公告)日：2014-07-01
申请号：US13345120
申请日：2012-01-06
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5227 , H01L21/76883 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。在第一线退火之后，形成与第一线垂直对准的第二线。形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。

2. 发明授权

US08642452B2 Semiconductor-on-insulator device with asymmetric structure 有权
公开(公告)号：US08642452B2
公开(公告)日：2014-02-04
申请号：US13012137
申请日：2011-01-24
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/36
CPC分类号： H01L27/0255 , G06F17/5022 , G06F17/5045 , H01L27/0262 , H01L27/1203 , H01L29/6609 , H01L29/66393 , H01L29/7436 , H01L29/861
摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

3. 发明授权

US08610249B2 Non-planar capacitor and method of forming the non-planar capacitor 有权
标题翻译：非平面电容器和非平面电容器的形成方法
公开(公告)号：US08610249B2
公开(公告)日：2013-12-17
申请号：US13434964
申请日：2012-03-30
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L21/845 , H01L27/1211 , H01L28/90 , H01L29/94
摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.
摘要翻译：这里公开了非平面电容器的实施例。非平面电容器可以包括在半导体衬底上方的多个鳍片。每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。门结构可以穿过翅片的中心部分。该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。

4. 发明授权

US08586466B2 Electrical fuse with a current shunt 有权
标题翻译：电保险丝与电流分路
公开(公告)号：US08586466B2
公开(公告)日：2013-11-19
申请号：US12967308
申请日：2010-12-14
申请人： Tom C. Lee , Thomas L. McDevitt , William J. Murphy
发明人： Tom C. Lee , Thomas L. McDevitt , William J. Murphy
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.
摘要翻译：电熔丝和形成电熔丝的方法。电熔丝包括通过图案化由第一导电材料构成的第一层并且设置在电介质层的顶表面上而形成的电流分流器。在电流分路上形成层叠层，并且在电流分路周围形成介电层的顶表面。层叠包括由第二导电材料构成的第二层和由第三导电材料构成的第三层。层叠体可以被图案化以限定作为层叠体的第一部分的熔丝链，其直接接触电介质层的顶表面，并且通过电流分路与端子作为与电介质层的顶表面分离的第二部分。

5. 发明授权

US08575718B2 Programmable electrical fuse 失效
标题翻译：可编程电气保险丝
公开(公告)号：US08575718B2
公开(公告)日：2013-11-05
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

6. 发明申请

US20130256835A1 NON-PLANAR CAPACITOR AND METHOD OF FORMING THE NON-PLANAR CAPACITOR 有权
标题翻译：非平面电容器和形成非平面电容器的方法
公开(公告)号：US20130256835A1
公开(公告)日：2013-10-03
申请号：US13434964
申请日：2012-03-30
申请人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/0805 , H01L21/845 , H01L27/1211 , H01L28/90 , H01L29/94
摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.
摘要翻译：这里公开了非平面电容器的实施例。非平面电容器可以包括在半导体衬底上方的多个鳍片。每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。门结构可以穿过翅片的中心部分。该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。

7. 发明授权

US08445355B2 Metal-insulator-metal capacitors with high capacitance density 有权
标题翻译：具有高电容密度的金属 - 绝缘体 - 金属电容器
公开(公告)号：US08445355B2
公开(公告)日：2013-05-21
申请号：US12969004
申请日：2010-12-15
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L28/82 , H01L23/5223 , H01L27/0207 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.
摘要翻译：金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

8. 发明授权

US08421128B2 Semiconductor device heat dissipation structure 失效
标题翻译：半导体器件散热结构
公开(公告)号：US08421128B2
公开(公告)日：2013-04-16
申请号：US11960030
申请日：2007-12-19
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L23/62
CPC分类号： H01L23/34 , H01L21/743 , H01L21/76877 , H01L21/84 , H01L23/3677 , H01L27/0255 , H01L27/1203 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.
摘要翻译：半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。

9. 发明申请

US20120287707A1 OPTOELECTRONIC MEMORY DEVICES 审中-公开
标题翻译：光电存储器件
公开(公告)号：US20120287707A1
公开(公告)日：2012-11-15
申请号：US13558541
申请日：2012-07-26
申请人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
发明人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.
摘要翻译：一个结构。该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

10. 发明申请

US20120257317A1 RC-triggered Semiconductor Controlled Rectifier for ESD Protection of Signal Pads 有权
标题翻译： RC触发半导体控制整流器用于信号垫的ESD保护
公开(公告)号：US20120257317A1
公开(公告)日：2012-10-11
申请号：US13079946
申请日：2011-04-05
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/04 , H05K13/00 , G06F17/50
CPC分类号： H02H9/046 , H01L27/0262 , H03K19/00361 , Y10T29/49002
摘要： RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.
摘要翻译：用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。

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