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1. 发明授权

US07512506B2 IC chip stress testing 失效
标题翻译： IC芯片压力测试
公开(公告)号：US07512506B2
公开(公告)日：2009-03-31
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流Is; 并且在施加恒定电流Is的同时对线进行应力测试，使得恒定电流Is不会由于电迁移开始时的电阻变化而改变。

2. 发明申请

US20080297188A1 IC CHIP STRESS TESTING 失效
标题翻译： IC芯片应力测试
公开(公告)号：US20080297188A1
公开(公告)日：2008-12-04
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

3. 发明授权

US08018017B2 Thermo-mechanical cleavable structure 有权
标题翻译：热机械可切割结构
公开(公告)号：US08018017B2
公开(公告)日：2011-09-13
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
发明人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
IPC分类号： H01L31/058
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

4. 发明授权

US07692439B2 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US07692439B2
公开(公告)日：2010-04-06
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

5. 发明申请

US20090230555A1 TUNGSTEN LINER FOR ALUMINUM-BASED ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE 审中-公开
标题翻译：基于铝的电阻互连结构的TUNGSTEN LINER
公开(公告)号：US20090230555A1
公开(公告)日：2009-09-17
申请号：US12049698
申请日：2008-03-17
申请人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
发明人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53223 , H01L23/5329 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.
摘要翻译：在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。一种金属层堆叠，包括从底部到顶部的低氧反应性金属层，底部过渡金属层，底部过渡金属氮化物层，铝 - 铜层，任选的顶部过渡金属层和顶部过渡层金属氮化物层。金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和电介质材料层之间的化合物的形成，因此提高了至少一种铝基金属线的电迁移率不与介电材料层相互作用。

6. 发明申请

US20090183131A1 STRUCTURE FOR SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY 有权
标题翻译：半导体芯片修复方案结构的负偏差温度不稳定性
公开(公告)号：US20090183131A1
公开(公告)日：2009-07-16
申请号：US12050990
申请日：2008-03-19
申请人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
发明人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L23/345 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.
摘要翻译：公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。修理方案在每个设备上使用加热元件。加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

7. 发明申请

US20080231312A1 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

8. 发明授权

US07890893B2 Design structure for semiconductor on-chip repair scheme for negative bias temperature instability 有权
标题翻译：用于负偏压温度不稳定性的半导体片上修复方案的设计结构
公开(公告)号：US07890893B2
公开(公告)日：2011-02-15
申请号：US12050990
申请日：2008-03-19
申请人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
发明人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L23/345 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.
摘要翻译：公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。修理方案在每个设备上使用加热元件。加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

9. 发明授权

US07838958B2 Semiconductor on-chip repair scheme for negative bias temperature instability 有权
标题翻译：半导体片上修复方案负偏温度不稳定性
公开(公告)号：US07838958B2
公开(公告)日：2010-11-23
申请号：US11971937
申请日：2008-01-10
申请人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
发明人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
IPC分类号： H01L31/058 , H01L37/00 , H01L21/00
CPC分类号： H01L23/345 , H01L22/14 , H01L22/20 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.
摘要翻译：公开了半导体芯片结构的实施例和一种对于由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件而并入局部的片上修复方案的方法。修理方案在每个设备上使用加热元件。加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

10. 发明授权

US07768815B2 Optoelectronic memory devices 失效
标题翻译：光电存储器件
公开(公告)号：US07768815B2
公开(公告)日：2010-08-03
申请号：US11161941
申请日：2005-08-23
申请人： Fen Chen , Richard S. Kontra , Tom C. Lee , Theodore M. Levin , Christopher D. Muzzy , Timothy D. Sullivan
发明人： Fen Chen , Richard S. Kontra , Tom C. Lee , Theodore M. Levin , Christopher D. Muzzy , Timothy D. Sullivan
IPC分类号： G11C13/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.
摘要翻译：一种结构及其操作方法。该方法包括在衬底上提供电阻/反射区域，其中电阻/反射区域包括具有由于材料吸收热而改变材料的反射率的特性的材料; 发送电流通过电阻/反射区域，以使电阻/反射区域的反射率变化从第一反射率值到不同于第一反射率值的第二反射率值; 并且光学地读取电阻/反射区域中的反射率变化。

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