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1. 发明授权

US5534462A Method for forming a plug and semiconductor device having the same 失效
标题翻译：用于形成插头的方法和具有该插头的半导体器件
公开(公告)号：US5534462A
公开(公告)日：1996-07-09
申请号：US393782
申请日：1995-02-24
申请人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein , Bernard J. Roman
发明人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein , Bernard J. Roman
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/7684 , H01L21/76802 , H01L21/76829 , H01L21/7685 , H01L21/76877 , Y10S438/959
摘要： A conductive plug (46) is formed in a semiconductor device (30) by using an aluminum nitride glue layer (42). The glue layer is deposited on an interlayer dielectric (40) prior to forming a contact opening (44), such that the glue layer does not line the opening sidewalls or bottom. Tungsten or other plug material is then deposited in the opening and on the glue layer and subsequently polished or etched back to form the plug. The remaining portions of the glue layer may be left within the device or removed as deemed appropriate.
摘要翻译：通过使用氮化铝胶层（42）在半导体器件（30）中形成导电插塞（46）。在形成接触开口（44）之前，胶层沉积在层间电介质（40）上，使得胶层不与开口侧壁或底部对齐。然后将钨或其他塞子材料沉积在开口和胶层上，随后抛光或回蚀以形成塞子。胶层的剩余部分可以留在装置内或者视为适当的去除。

2. 发明授权

US5525542A Method for making a semiconductor device having anti-reflective coating 失效
标题翻译：制造具有抗反射涂层的半导体器件的方法
公开(公告)号：US5525542A
公开(公告)日：1996-06-11
申请号：US393781
申请日：1995-02-24
申请人： Papu D. Maniar , Robert W. Fiordalice , Kevin G. Kemp , Bernard J. Roman
发明人： Papu D. Maniar , Robert W. Fiordalice , Kevin G. Kemp , Bernard J. Roman
IPC分类号： G03F7/004 , G03F7/20 , H01L21/027 , H01L21/28
CPC分类号： H01L21/0276 , Y10S148/113 , Y10S438/952
摘要： An anti-reflective coating (ARC) (20) is formed over a reflective, conductive layer (18), such as polysilicon or aluminum, in a semiconductor device (10). The ARC is an aluminum nitride layer. During photolithography, the ARC absorbs radiation waves (30), particularly absorbing wavelengths under 300 nanometers, such as deep ultraviolet (DUV) radiation at 248 nanometers. Being absorbed by the ARC, the radiation waves are prevented from reflecting off the underlying conductive layer. Thus, resist mask (34) is patterned and developed true to the pattern on lithography mask (24), resulting in accurate replication into appropriate layers of the device.
摘要翻译：在半导体器件（10）中的反射导电层（18）（例如多晶硅或铝）上形成抗反射涂层（ARC）（20）。 ARC是氮化铝层。在光刻期间，ARC吸收辐射波（30），特别是吸收在300纳米以下的波长，例如248纳米的深紫外（DUV）辐射。被ARC吸收，辐射波被防止从下面的导电层反射出来。因此，抗蚀剂掩模（34）被图案化并且在光刻掩模（24）上的图案上真实地形成，导致准确地复制到器件的适当层中。

3. 发明授权

US5918147A Process for forming a semiconductor device with an antireflective layer 失效
标题翻译：用于形成具有抗反射层的半导体器件的工艺
公开(公告)号：US5918147A
公开(公告)日：1999-06-29
申请号：US413021
申请日：1995-03-29
申请人： Stanley M. Filipiak , Ted R. White , T. P. Ong , Jung-Hui Lin , Wayne M. Paulson , Bernard J. Roman
发明人： Stanley M. Filipiak , Ted R. White , T. P. Ong , Jung-Hui Lin , Wayne M. Paulson , Bernard J. Roman
IPC分类号： G03F7/11 , H01L21/027 , H01L21/285 , H01L21/316 , H01L21/318 , H01L21/3213
CPC分类号： H01L21/28512 , H01L21/0276 , H01L21/31604 , H01L21/3185 , H01L21/32133
摘要： Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.
摘要翻译：已经开发了具有离散部分（541,542,861,862,863,1091和1092）的抗反射层（54,86和109）。离散部分（541,542,861,862,863,1091和1092）允许在许多情况下使用抗反射层（54,86和109），其中使用均匀组成的单层将是困难的或不可能的。或者，可以使用具有连续渐变组成的单个抗反射层。

4. 发明授权

US5085230A Smoker's appliance 失效
标题翻译：吸烟者的家电
公开(公告)号：US5085230A
公开(公告)日：1992-02-04
申请号：US581807
申请日：1990-09-13
申请人： Bernard J. Roman
发明人： Bernard J. Roman
IPC分类号： A24F19/14
CPC分类号： A24F19/14
摘要： A smoker's appliance for the reduction of a quantity of smoke emanating from a lighted cigarette during periods of time the lighted cigarette is not being smoked includes a hollow support body having a bottom edge for engaging a supporting surface and a wall with a plurality of retaining apertures formed therein, a plurality of receptacle for retaining cigarettes, each receptacle having a generally tubular body with a cylindrical outer surface and a longitudinally extending aperture of polygonal cross section extending between an outer end and an inner end of the tubular body and a fastener for maintaining each of the receptacles in an associated one of the retaining apertures whereby heat energy from the lighted end of a cigarette inserted in one of the receptacles is dissipated through the tubular body and the amount of oxygen supplied to the cigarette is decreased. The support body can be frustum shaped with an open top and bottom and formed of a plastic material while the receptacles are formed of a metal material. The receptacle tubular body has a radially outwardly extending flange formed at the outer end and a chamfer formed on the flange at an entrance to the longitudinally extending aperture for receiving a lighted end of a cigarette.
摘要翻译：一种用于在点燃的香烟未被吸烟的时段期间减少从点燃的香烟发出的烟雾量的吸烟者的装置包括具有用于接合支撑表面的底部边缘和具有多个保持孔的壁的中空支撑体多个用于保持香烟的容器，每个容器具有大致管状的本体，该管状体具有圆柱形外表面和在管状体的外端和内端之间延伸的多边形横截面的纵向延伸的孔，以及用于保持相应的一个保持孔中的每个容器，由此插入其中一个容器中的香烟的发光端的热能通过管状体散发，并且供应到香烟的氧气量减少。支撑体可以是具有敞开的顶部和底部的平截头体形状，并且由塑料材料形成，而容器由金属材料形成。插座管体具有形成在外端处的径向向外延伸的凸缘和在纵向延伸孔的入口处形成在凸缘上的倒角，用于接收香烟的点燃端。

5. 发明授权

US5292623A Method for forming integrated circuit devices using a phase shifting mask 失效
标题翻译：使用相移掩模形成集成电路器件的方法
公开(公告)号：US5292623A
公开(公告)日：1994-03-08
申请号：US907973
申请日：1992-07-02
申请人： Kevin G. Kemp , Bernard J. Roman
发明人： Kevin G. Kemp , Bernard J. Roman
IPC分类号： G03F1/30 , G03F7/00
CPC分类号： G03F7/2022 , G03F1/30
摘要： Integrated circuits with small feature sizes are obtained using a phase shifting mask which has reduced back reflection and improved optical contrast. These improvements result from reduced etching of the chrome and chrome oxide layers on the phase shifting mask. In one embodiment, the phase shifting mask is formed by depositing an image reversible photoresist layer (22) which overlies the optical mask (18). Forming a first exposed region (24) and an unexposed region (26) in the image reversible photoresist layer (22). Treating the first exposed region (24) to form a hardened first exposed region. Forming a second exposed region (30) within the remaining portion of the unexposed region (26) by exposing the back surface (16) of the substrate (12) to an optical illumination source. Removing the second exposed region (30) to uncover a portion (32) of the substrate (12) and to form an etch mask (34). The uncovered portion (32) of the substrate (12) is etched to form a trench region (38).
摘要翻译：使用具有减少的反射反射和改善的光学对比度的相移掩模获得具有小特征尺寸的集成电路。这些改进是由于减少相移掩模上的铬和铬氧化物层的蚀刻。在一个实施例中，通过沉积覆盖在光学掩模（18）上的图像可逆光致抗蚀剂层（22）形成相移掩模。在图像可逆光致抗蚀剂层（22）中形成第一曝光区域（24）和未曝光区域（26）。处理第一暴露区域（24）以形成硬化的第一暴露区域。通过将基板（12）的背面（16）暴露于光照明源，在未曝光区域（26）的剩余部分内形成第二曝光区域（30）。移除第二暴露区域（30）以露出衬底（12）的一部分（32）并形成蚀刻掩模（34）。蚀刻衬底（12）的未覆盖部分（32）以形成沟槽区域（38）。

6. 发明授权

US4959326A Fabricating T-gate MESFETS employing double exposure, double develop techniques 失效
标题翻译：采用双重曝光，双重开发技术制造T栅极MESFETS
公开(公告)号：US4959326A
公开(公告)日：1990-09-25
申请号：US289071
申请日：1988-12-22
申请人： Bernard J. Roman , Richard E. Muller
发明人： Bernard J. Roman , Richard E. Muller
IPC分类号： H01L21/285 , H01L21/338
CPC分类号： H01L29/66863 , H01L21/28587
摘要： A method for forming a T-gate for a MESFET device comprises a double exposure, double develop process. In a first exposure employing lithography a layer of PMMA is applied first to a substrate and spun to a desired thickness and then baked for a predetermined period. The gate pattern was aligned to the ohmic level and either E-beam written or exposed to deep UV radiation through a quartz mask. The wafer as treated was then spray developed using a mixture of MIBK and alcohol. After coating with a Novolak resist, the same gate mask was either realigned to the Ohmic level and exposed to mid-range UV radiation in the 400 nm range or alternatively E-beam written with a modified gate pattern to eliminate the T at the gate pad. The wafer was then spray developed again, this time using LSI developer. The second photo was overexposed in order to form a large opening through the top of the T while the first photo was underexposed to make the stem of the T as narrow as possible. After an oxygen plasma descum, the wafer was spray etched with a suitable solution and then rinsed. The resultant wafer possessed a T-shaped recess for the gate configuration which then was conventionally metallized to form MESFETS.
摘要翻译：用于形成MESFET器件的T形栅极的方法包括双曝光，双重显影工艺。在使用平版印刷术的第一曝光中，首先将一层PMMA施加到基底上并纺丝至所需厚度，然后烘烤预定时间。栅极图案与欧姆级对准，电子束被写入或暴露于通过石英掩模的深紫外线辐射。然后使用MIBK和醇的混合物将处理的晶片喷雾显影。在用酚醛清漆抗蚀剂涂覆之后，将相同的栅极掩模重新对准欧姆水平并暴露于400nm范围内的中等范围的UV辐射，或者以修改的栅极图案写入电子束，以消除栅极焊盘处的T 。然后将晶片再次喷涂，此时使用LSI开发商。第二张照片曝光过度，以形成通过T顶部的大开口，而第一张照片曝光不足，使得T杆尽可能窄。在氧等离子体除去之后，用合适的溶液喷涂晶片，然后冲洗。所得到的晶片具有用于栅极配置的T形凹槽，然后通常将其金属化以形成MESFETS。

7. 发明授权

US08230628B2 Apparatus and method for attaching signs to concrete road barriers 有权
标题翻译：将标志贴到混凝土路障上的装置和方法
公开(公告)号：US08230628B2
公开(公告)日：2012-07-31
申请号：US12751097
申请日：2010-03-31
申请人： Michael J. Recker , Raymond R. Sullivan , Bernard J. Roman
发明人： Michael J. Recker , Raymond R. Sullivan , Bernard J. Roman
IPC分类号： G09F7/18
CPC分类号： E01F9/669 , Y10T29/49963
摘要： A mounting arrangement for securing signs at select positions along the length of a concrete barrier is provided by forming a longitudinally extending groove within one side of the barrier and slideably positioning a bolt within the channel so that the bolt is captured within the channel for longitudinal movement relative thereto and extends through the groove and to the exterior of the barrier. The bolt extends through a sign support on the exterior of the barrier. A nut engaged with the bolt draws the sign support into secure engagement with the exterior surface of the barrier.
摘要翻译：通过在屏障的一侧形成纵向延伸的凹槽，并将螺栓可滑动地定位在通道内，以使得螺栓被捕获在通道内用于纵向移动，从而提供沿着混凝土屏障的长度将符号固定在选定位置的安装装置相对于此并且延伸穿过凹槽并且延伸到屏障的外部。螺栓延伸穿过屏障外部的标志支架。与螺栓接合的螺母将标志支撑件与屏障的外表面牢固地接合。

8. 发明授权

US06586160B2 Method for patterning resist 有权
公开(公告)号：US06586160B2
公开(公告)日：2003-07-01
申请号：US09817408
申请日：2001-03-26
申请人： Chung-Peng Ho , Bernard J. Roman , Chong-Cheng Fu
发明人： Chung-Peng Ho , Bernard J. Roman , Chong-Cheng Fu
IPC分类号： G03F720
CPC分类号： G03F7/70333 , G03F7/70358
摘要： A resist layer (34) on a semiconductor wafer (20) is patterned by using a scanning exposure system (50) which provides light, containing pattern information which is intended to be transferred to the wafer. The lithographic system is a step and scan system in which a reticle (16) passes between a light source and a lens system(18). The wafer with the resist layer is passed through a focal plane of the patterned light at a tilt angle (&thgr;). The user selects a desirable range for the depth of the resist to be exposed at the focus of the patterned light. The tilt angle is calculated by taking the arc tangent of the desirable range divided by a width of a slit region (52) of the projected light. The depth of focus increases over standard step and scan techniques.

9. 发明授权

US5827625A Methods of designing a reticle and forming a semiconductor device therewith 失效
标题翻译：设计掩模版并与其形成半导体器件的方法
公开(公告)号：US5827625A
公开(公告)日：1998-10-27
申请号：US912601
申请日：1997-08-18
申请人： Kevin Lucas , Michael E. Kling , Bernard J. Roman , Alfred J. Reich
发明人： Kevin Lucas , Michael E. Kling , Bernard J. Roman , Alfred J. Reich
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F1/36
摘要： A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device features. The width of the outriggers can be changed based on pitch and location between features in a semi-dense or dense feature pattern. In one embodiment, the outriggers can be manually or automatically inserted into the layout file after the locations of the attenuating features have been determined. The outriggers are not patterned on the substrate, but assist in forming resist features of uniform width.
摘要翻译：一种用于设计和形成掩模版（40）的方法以及使用该掩模版（40）制造半导体衬底（50）。本发明在密集和半致密特征图案中的特征（30）之间放置支架（32,34,36），以有助于图案化装置特征。外悬支架的宽度可以基于半密集或密集特征图案中的特征之间的间距和位置来改变。在一个实施例中，在已经确定衰减特征的位置之后，外伸支架可以手动地或自动地插入到布局文件中。外延支架不在基板上图案化，但有助于形成均匀宽度的抗蚀剂特征。

10. 发明授权

US5539249A Method and structure for forming an integrated circuit pattern on a semiconductor substrate 失效
公开(公告)号：US5539249A
公开(公告)日：1996-07-23
申请号：US309231
申请日：1994-09-20
申请人： Bernard J. Roman , Bich-Yen Nguyen , Chandrasekaram Ramiah
发明人： Bernard J. Roman , Bich-Yen Nguyen , Chandrasekaram Ramiah
IPC分类号： G03F7/11 , G03F7/09 , G03F7/20 , H01L21/027 , H01L23/58
CPC分类号： G03F7/70583 , G03F7/091 , G03F7/70441 , G03F7/70691 , H01L21/0276 , Y10S438/952
摘要： Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is formed over the reflective materials and a layer of photoresist is then formed over the silicon-rich silicon nitride. The photoresist layer is then photolithographically patterned to form an integrated circuit pattern (20). The silicon-rich silicon nitride layer has an absorptive index of greater than 0.25, which allows it to be used as an anti-reflective layer with photolithographic patterning systems having ultraviolet and deep ultraviolet exposure wavelengths.

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