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1. 发明授权

US5525542A Method for making a semiconductor device having anti-reflective coating 失效
标题翻译：制造具有抗反射涂层的半导体器件的方法
公开(公告)号：US5525542A
公开(公告)日：1996-06-11
申请号：US393781
申请日：1995-02-24
申请人： Papu D. Maniar , Robert W. Fiordalice , Kevin G. Kemp , Bernard J. Roman
发明人： Papu D. Maniar , Robert W. Fiordalice , Kevin G. Kemp , Bernard J. Roman
IPC分类号： G03F7/004 , G03F7/20 , H01L21/027 , H01L21/28
CPC分类号： H01L21/0276 , Y10S148/113 , Y10S438/952
摘要： An anti-reflective coating (ARC) (20) is formed over a reflective, conductive layer (18), such as polysilicon or aluminum, in a semiconductor device (10). The ARC is an aluminum nitride layer. During photolithography, the ARC absorbs radiation waves (30), particularly absorbing wavelengths under 300 nanometers, such as deep ultraviolet (DUV) radiation at 248 nanometers. Being absorbed by the ARC, the radiation waves are prevented from reflecting off the underlying conductive layer. Thus, resist mask (34) is patterned and developed true to the pattern on lithography mask (24), resulting in accurate replication into appropriate layers of the device.
摘要翻译：在半导体器件（10）中的反射导电层（18）（例如多晶硅或铝）上形成抗反射涂层（ARC）（20）。 ARC是氮化铝层。在光刻期间，ARC吸收辐射波（30），特别是吸收在300纳米以下的波长，例如248纳米的深紫外（DUV）辐射。被ARC吸收，辐射波被防止从下面的导电层反射出来。因此，抗蚀剂掩模（34）被图案化并且在光刻掩模（24）上的图案上真实地形成，导致准确地复制到器件的适当层中。

2. 发明授权

US5534462A Method for forming a plug and semiconductor device having the same 失效
标题翻译：用于形成插头的方法和具有该插头的半导体器件
公开(公告)号：US5534462A
公开(公告)日：1996-07-09
申请号：US393782
申请日：1995-02-24
申请人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein , Bernard J. Roman
发明人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein , Bernard J. Roman
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/7684 , H01L21/76802 , H01L21/76829 , H01L21/7685 , H01L21/76877 , Y10S438/959
摘要： A conductive plug (46) is formed in a semiconductor device (30) by using an aluminum nitride glue layer (42). The glue layer is deposited on an interlayer dielectric (40) prior to forming a contact opening (44), such that the glue layer does not line the opening sidewalls or bottom. Tungsten or other plug material is then deposited in the opening and on the glue layer and subsequently polished or etched back to form the plug. The remaining portions of the glue layer may be left within the device or removed as deemed appropriate.
摘要翻译：通过使用氮化铝胶层（42）在半导体器件（30）中形成导电插塞（46）。在形成接触开口（44）之前，胶层沉积在层间电介质（40）上，使得胶层不与开口侧壁或底部对齐。然后将钨或其他塞子材料沉积在开口和胶层上，随后抛光或回蚀以形成塞子。胶层的剩余部分可以留在装置内或者视为适当的去除。

3. 发明授权

US5677231A Method for providing trench isolation 失效
标题翻译：提供沟槽隔离的方法
公开(公告)号：US5677231A
公开(公告)日：1997-10-14
申请号：US656817
申请日：1996-06-03
申请人： Papu D. Maniar , Robert W. Fiordalice
发明人： Papu D. Maniar , Robert W. Fiordalice
IPC分类号： H01L21/28 , H01L21/60 , H01L21/762 , H01L21/768 , H01L21/76
CPC分类号： H01L21/76897 , H01L21/28 , H01L21/76224 , H01L21/76802 , Y10S148/02 , Y10S438/97
摘要： A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region. (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.
摘要翻译：制造沟槽隔离区域（32）以包括由氮化铝构成的沟槽衬垫（28）。氮化铝沟槽衬套可用于无边界接触应用中，其中在层间电介质（54）中蚀刻接触开口（56）并覆盖有源区域。（例如，掺杂区域52）和沟槽隔离区域。在使用对氮化铝有选择性的蚀刻化学形成开口期间，沟槽衬垫保护沟槽的拐角区域（58）处的P-N结以防止接合。通过保护接头，随后形成导电插塞（60）将不会使接头电短路，并将二极管泄漏保持在可接受的水平内。

4. 发明授权

US5652176A Method for providing trench isolation and borderless contact 失效
标题翻译：提供沟槽隔离和无边界接触的方法
公开(公告)号：US5652176A
公开(公告)日：1997-07-29
申请号：US393783
申请日：1995-02-24
申请人： Papu D. Maniar , Robert W. Fiordalice
发明人： Papu D. Maniar , Robert W. Fiordalice
IPC分类号： H01L21/28 , H01L21/60 , H01L21/762 , H01L21/768 , H01L21/76
CPC分类号： H01L21/76897 , H01L21/28 , H01L21/76224 , H01L21/76802 , Y10S148/02 , Y10S438/97
摘要： A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.
摘要翻译：制造沟槽隔离区域（32）以包括由氮化铝构成的沟槽衬垫（28）。氮化铝沟槽衬垫可用于无边界接触应用中，其中在层间电介质（54）中蚀刻接触开口（56）并覆盖有源区域（例如，掺杂区域52）和沟槽隔离区域两者。在使用对氮化铝有选择性的蚀刻化学形成开口形成期间，沟槽衬垫保护沟槽的拐角区域（58）处的P-N结以防止接合。通过保护接头，随后形成导电插塞（60）将不会使接头电短路，并将二极管泄漏保持在可接受的水平内。

5. 发明授权

US5578523A Method for forming inlaid interconnects in a semiconductor device 失效
标题翻译：在半导体器件中形成镶嵌互连的方法
公开(公告)号：US5578523A
公开(公告)日：1996-11-26
申请号：US444184
申请日：1995-05-18
申请人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein
发明人： Robert W. Fiordalice , Papu D. Maniar , Jeffrey L. Klein
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/7684 , H01L21/76802 , H01L21/76829 , H01L21/7685 , H01L21/76877 , Y10S438/959
摘要： In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect upon polishing. By allowing the sacrificial polish assisting layer (31) to be removed at close to the same rate as interconnect metal (42) during the final stages of polishing, dishing is avoided. The aluminum nitride layer also facilitates chemical vapor deposition of aluminum as the interconnect metal by providing a more suitable nucleation site for aluminum than exists with silicon dioxide.
摘要翻译：在本发明中，镶嵌互连（44）通过化学机械抛光形成。在层间电介质（30）和互连金属（42）之间形成呈氮化铝层形式的抛光辅助层（31），以防止在研磨时互连件的凹陷或凹陷。通过在抛光的最后阶段允许牺牲抛光辅助层（31）以与互连金属（42）相同的速率被去除，因此避免了凹陷。氮化铝层还通过为存在二氧化硅提供比铝更合适的成核位置，促进铝作为互连金属的化学气相沉积。

6. 发明授权

US07320931B2 Interfacial layer for use with high k dielectric materials 有权
标题翻译：用于高k电介质材料的界面层
公开(公告)号：US07320931B2
公开(公告)日：2008-01-22
申请号：US10903841
申请日：2004-07-30
申请人： Shawn G. Thomas , Vida Ilderem , Papu D. Maniar
发明人： Shawn G. Thomas , Vida Ilderem , Papu D. Maniar
IPC分类号： H01L29/72
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/02175 , H01L21/0237 , H01L21/02532 , H01L21/02617 , H01L21/02664 , H01L21/28255 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 Å, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.
摘要翻译：提供了用于在硅衬底上沉积纯锗罐的层的方法和装置。该锗层非常薄，约为14埃，并且小于硅上的纯锗的临界厚度。锗层用作硅衬底和沉积在锗层上的高k栅极层之间的中间层。锗层有助于避免在施加高k材料时氧化物界面层的发展。锗中间层在半导体结构中的应用导致高k栅极功能，而不会由于氧化物杂质而导致串联电容的缺点。锗层进一步提高了移动性。

7. 发明授权

US6127257A Method of making a contact structure 失效
标题翻译：制作接触结构的方法
公开(公告)号：US6127257A
公开(公告)日：2000-10-03
申请号：US154366
申请日：1993-11-18
申请人： Faivel S. Pintchovski , John R. Yeargain , Papu D. Maniar
发明人： Faivel S. Pintchovski , John R. Yeargain , Papu D. Maniar
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/76852 , H01L21/76885 , H01L23/5226 , H01L2221/1078 , H01L23/53223 , H01L23/53257 , H01L2924/0002
摘要： An improved contact structure and process for forming an improved contact structure for a semiconductor device. A metal (14) is formed on a first metal layer (12) positioned on a substrate (10) The metal (14) is a Group VIIB or Group VIII metal or metal oxide and increases the electrically conductive surface area (25) of the first metal layer (12). In one embodiment, a Group VIIB or Group VIII metal layer is deposited onto the first metal layer and the Group VIIB or Group VIII metal layer is anisotropically etched to form sidewall spacers (24). An insulating layer (16) is deposited overlying the first conductive layer (12) and the sidewall spacers (24). A via opening (18) is formed in the insulation layer (16) to expose a portion of the electrically conductive surface area (25). A second metal layer (22) fills the opening (18) and forms a metallurgical contact to the first metal layer (12).
摘要翻译：用于形成用于半导体器件的改进的接触结构的改进的接触结构和工艺。在位于基板（10）上的第一金属层（12）上形成金属（14）。金属（14）是VIIB族或VIII族金属或金属氧化物，并且增加了导电表面积（25）第一金属层（12）。在一个实施方案中，将第VIIB族或第VIII族金属层沉积到第一金属层上，并且第VIIB族或第VIII族金属层被各向异性蚀刻以形成侧壁间隔物（24）。绝缘层（16）沉积在第一导电层（12）和侧壁间隔物（24）上。在绝缘层（16）中形成通孔（18），以暴露导电表面区域（25）的一部分。第二金属层（22）填充开口（18）并与第一金属层（12）形成冶金接触。

8. 发明授权

US5910680A Germanium silicate spin on glass semiconductor device and methods of spin on glass synthesis and use 失效
标题翻译：玻璃硅酸盐旋涂玻璃半导体器件及玻璃合成和使用方法
公开(公告)号：US5910680A
公开(公告)日：1999-06-08
申请号：US215170
申请日：1994-03-21
申请人： Papu D. Maniar
发明人： Papu D. Maniar
IPC分类号： H01L21/316 , H01L23/58
CPC分类号： H01L21/316
摘要： A semiconductor device (11) has a spin on glass layer or region, and the spin on glass has a method of synthesis and use. The spin on glass composition is formed which comprises on the order of 0% to 20% by volume of tetraethylorthosilicate (TEOS), on the order of 0.01% to 20% by volume of tetraethylorthogermanate (TEOG), on the order of 0% to 1% by volume the equivalent of nitric acid (HNO.sub.3), on the order of 70% to 85% by volume of alcohol, and a remaining balance of the spin on glass composition being water. The spin on glass is applied to a semiconductor substrate and heated and/or densified to form the spin on glass layer or region.
摘要翻译：半导体器件（11）具有在玻璃层或区域上的自旋，并且玻璃上的旋涂具有合成和使用的方法。形成旋涂玻璃组合物，其含量为约0〜20体积％的原硅酸四乙酯（TEOS），为约0.01-20体积％的四乙基原硅酸酯（TEOG），为0〜相当于硝酸（HNO 3）1体积％，醇的体积百分数为70〜85体积％，玻璃组合物的旋转余量为水。将玻璃上的旋涂施加到半导体衬底上并加热和/或致密化以在玻璃层或区域上形成自旋。

9. 发明授权

US5702981A Method for forming a via in a semiconductor device 失效
标题翻译：在半导体器件中形成通孔的方法
公开(公告)号：US5702981A
公开(公告)日：1997-12-30
申请号：US536537
申请日：1995-09-29
申请人： Papu D. Maniar , Roc Blumenthal , Jeffrey L. Klein , Wei Wu
发明人： Papu D. Maniar , Roc Blumenthal , Jeffrey L. Klein , Wei Wu
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76834 , Y10S438/97
摘要： A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, is deposited over conductive interconnect (34). A via (44) is etched in interlayer dielectric (42), stopping on etch stop layer (40). Etch stop layer (40) is then anisotropicly etched to expose the top of conductive interconnect (34), while maintaining a portion of the etch stop layer along a sidewall of the interconnect, and particularly along those sidewall portions which contain aluminum. A conductive plug (54) is then formed in the via, preferably using one or more barrier or glue layers (50). Formation of a tungsten plug using tungsten hexafluoride can then be performed without unwanted reactions between the tungsten source gas and the aluminum interconnect.
摘要翻译：用于在半导体器件中形成通孔的方法通过在通孔形成工艺期间通过使用蚀刻停止层来改善形成的触点的电阻和可靠性。蚀刻停止层（40），优选氮化硅或氮化铝层，沉积在导电互连（34）上。在层间电介质（42）中蚀刻通孔（44），停止在蚀刻停止层（40）上。然后对蚀刻停止层（40）进行各向异性蚀刻以暴露导电互连（34）的顶部，同时沿着互连的侧壁，特别是沿着包含铝的侧壁部分保留蚀刻停止层的一部分。然后，优选地使用一个或多个阻挡层或胶层（50）在通孔中形成导电插塞（54）。然后可以进行使用六氟化钨形成钨塞，而不会在钨源气体和铝互连之间产生不必要的反应。

10. 发明申请

US20130147850A1 METHOD AND DEVICE FOR FORCE SENSING GESTURE RECOGNITION 审中-公开
标题翻译：用于感觉手势识别的方法和装置
公开(公告)号：US20130147850A1
公开(公告)日：2013-06-13
申请号：US13314265
申请日：2011-12-08
申请人： Hao Li , Papu D. Maniar , Yi Wei
发明人： Hao Li , Papu D. Maniar , Yi Wei
IPC分类号： G09G5/00
CPC分类号： G06F3/017 , G06F1/1694 , G06F3/0346 , G06F3/0414 , G06F3/0485
摘要： A method and device for force sensing gesture recognition includes a processor, a motion detector, and a force detector. A motion detector senses a motion of the mobile device corresponding to a gesture and generates gesture data, the gesture data indicative of a command to be executed. A force sensor senses a magnitude of applied force and generates force data. The magnitude of applied force is indicative of a mode in which the command is to be executed. The processor is coupled to the motion detector and the force sensor. The processor executes the command as a function of the gesture data and the force data.
摘要翻译：用于力感测手势识别的方法和装置包括处理器，运动检测器和力检测器。运动检测器感测与手势相对应的移动装置的运动，并生成指示要执行的命令的手势数据。力传感器感测施加的力的大小并产生力数据。施加力的大小表示要执行命令的模式。处理器耦合到运动检测器和力传感器。处理器根据手势数据和力数据执行命令。

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