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1. 发明申请

US20060136861A1 Layout modification using multilayer-based constraints 有权
标题翻译：使用基于多层次约束的布局修改
公开(公告)号：US20060136861A1
公开(公告)日：2006-06-22
申请号：US11018637
申请日：2004-12-21
申请人： Kevin Lucas , Robert Boone , Mehul Shroff , Kirk Strozewski , Chi-Min Yuan , Jason Porter
发明人： Kevin Lucas , Robert Boone , Mehul Shroff , Kirk Strozewski , Chi-Min Yuan , Jason Porter
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.
摘要翻译：一种用于改进设计的可制造性的方法包括在布局设计的多个交互层上执行空间或外壳检查，然后使用所得到的空间或外壳数据来移动改变的设计数据库中的预定特征边缘以降低特征宽度，特征图案的空间或特征外壳图案比设计的小。在一些实施例中，晶片电路图案中的大尺寸特征比在设计的数据库中绘制的特征更大。在一些实施例中，用于提高设计的可制造性的方法被存储在计算机可读存储介质上。

2. 发明授权

US5741626A Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) 失效
标题翻译：形成作为抗反射涂层（ARC）的电介质氮化钽层的方法
公开(公告)号：US5741626A
公开(公告)日：1998-04-21
申请号：US632209
申请日：1996-04-15
申请人： Ajay Jain , Kevin Lucas
发明人： Ajay Jain , Kevin Lucas
IPC分类号： G03F7/09 , H01L21/027 , H01L21/768 , G03F7/00 , H01L21/314
CPC分类号： H01L21/76829 , G03F7/091 , H01L21/0276 , H01L21/76807 , H01L21/7681 , H01L21/76813
摘要： The present invention provides an anti-reflective Ta.sub.3 N.sub.5 coating which can be used in a dual damascene structure and for I line or G line lithographies. In addition, the Ta.sub.3 N.sub.5 coating may also be used as an etch stop and a barrier layer. A dual damascene structure is formed by depositing a first dielectric layer (16). A dielectric tantalum nitride layer (18) is deposited on top of the first dielectric layer. A second dielectric layer (20) is deposited on the tantalum nitride layer. A dual damascene opening (34) is etched into the dielectric layers by patterning a first opening portion (26) and a second opening portion (32) using photolithography operations. Dielectric tantalum nitride layer (18) serves as an ARC layer during these operations to reduce the amount of reflectance from conductive region (14) to reduce distortion of the photoresist pattern. The use of a dielectric tantalum nitride layer as an ARC is particularly suitable for I line and G line lithography.
摘要翻译：本发明提供了可用于双镶嵌结构和I线或G线平版印刷的抗反射Ta3N5涂层。此外，Ta3N5涂层也可以用作蚀刻停止层和阻挡层。通过沉积第一介电层（16）形成双镶嵌结构。电介质氮化钽层（18）沉积在第一介电层的顶部。第二介电层（20）沉积在氮化钽层上。通过使用光刻操作图案化第一开口部分（26）和第二开口部分（32），将双镶嵌开口（34）蚀刻到电介质层中。在这些操作期间，介电氮化钽层（18）用作ARC层，以减少来自导电区域（14）的反射率，以减少光致抗蚀剂图案的变形。使用电介质氮化钽层作为ARC特别适用于I线和G线光刻。

3. 发明授权

US07962868B2 Method for forming a semiconductor device using optical proximity correction for the optical lithography 有权
标题翻译：使用光学光刻的光学邻近校正来形成半导体器件的方法
公开(公告)号：US07962868B2
公开(公告)日：2011-06-14
申请号：US12091695
申请日：2005-10-28
申请人： Kevin Lucas , Robert Boone , Karl Wimmer , Christian Gardin
发明人： Kevin Lucas , Robert Boone , Karl Wimmer , Christian Gardin
IPC分类号： G06F17/50 , G06K9/00 , G06K9/64
CPC分类号： G03F7/705 , G03F1/36
摘要： A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.
摘要翻译：一种用于形成半导体器件的方法包括执行特征片段的第一边缘位置的第一优化，其中第一优化具有每个片段的第一速度，并且执行特征片段的第二边缘位置的第二优化，其中第二优化具有比每个片段的第一速度慢的每个片段的第二速度。接下来，使用第二优化的结果来形成掩模版图案; 并且使用掩模版图案对半导体晶片上的层进行图案化。

4. 发明申请

US20080295060A1 Method for Forming a Semiconductor Device Using Optical Proximity Correction for the Optical Lithography 有权
标题翻译：用于光学光刻的光学接近校正形成半导体器件的方法
公开(公告)号：US20080295060A1
公开(公告)日：2008-11-27
申请号：US12091695
申请日：2005-10-28
申请人： Kevin Lucas , Robert Boone , Karl Wimmer , Christian Gardin
发明人： Kevin Lucas , Robert Boone , Karl Wimmer , Christian Gardin
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F1/36
摘要： A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.
摘要翻译：一种用于形成半导体器件的方法包括执行特征片段的第一边缘位置的第一优化，其中第一优化具有每个片段的第一速度，并且执行特征片段的第二边缘位置的第二优化，其中第二优化具有比每个片段的第一速度慢的每个片段的第二速度。接下来，使用第二优化的结果来形成掩模版图案; 并且使用掩模版图案对半导体晶片上的层进行图案化。

5. 发明申请

US20050087870A1 Semiconductor device and method of forming the same 有权
公开(公告)号：US20050087870A1
公开(公告)日：2005-04-28
申请号：US10691984
申请日：2003-10-23
申请人： Olubunmi Adetutu , Kevin Lucas
发明人： Olubunmi Adetutu , Kevin Lucas
IPC分类号： H01L21/28 , H01L21/4763 , H01L23/48 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) layer overlying and in physical contact with the barrier layer.

6. 发明授权

US5958635A Lithographic proximity correction through subset feature modification 失效
标题翻译：通过子集特征修改进行平版印刷邻近校正
公开(公告)号：US5958635A
公开(公告)日：1999-09-28
申请号：US954160
申请日：1997-10-20
申请人： Alfred John Reich , Hak-Lay Chuang , Michael E. Kling , Paul G. Y. Tsui , Kevin Lucas , James N. Conner
发明人： Alfred John Reich , Hak-Lay Chuang , Michael E. Kling , Paul G. Y. Tsui , Kevin Lucas , James N. Conner
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , G03F9/00
CPC分类号： G03F1/36 , G03F7/70425 , Y10S430/143
摘要： Lithographic Proximity Correction (LPC) shapes are added (503) to a layer of a layout database file (501). Geometric criteria such as feature width are then used to filter the added LPC shapes (502). The LPC shapes are then modified (505) by determining which LPC shapes are within a predetermined distance from a shape in a layer of the second data base (504). The database file, including the modified LPC shapes, is then used to manufacture a set of lithographic masks (506). The lithographic masks are then used to pattern a set of wafers in the manufacture of integrated circuits (507).
摘要翻译：将平版摄影校正（LPC）形状（503）添加到布局数据库文件（501）的层中。然后使用诸如特征宽度的几何标准来过滤所添加的LPC形状（502）。然后通过确定哪个LPC形状在距第二数据库（504）的层中的形状预定距离内来修改LPC形状（505）。然后，使用数据库文件（包括修改的LPC形状）来制造一组光刻掩模（506）。然后使用光刻掩模在集成电路的制造中对一组晶片进行图案化（507）。

7. 发明授权

US5827625A Methods of designing a reticle and forming a semiconductor device therewith 失效
标题翻译：设计掩模版并与其形成半导体器件的方法
公开(公告)号：US5827625A
公开(公告)日：1998-10-27
申请号：US912601
申请日：1997-08-18
申请人： Kevin Lucas , Michael E. Kling , Bernard J. Roman , Alfred J. Reich
发明人： Kevin Lucas , Michael E. Kling , Bernard J. Roman , Alfred J. Reich
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F1/36
摘要： A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device features. The width of the outriggers can be changed based on pitch and location between features in a semi-dense or dense feature pattern. In one embodiment, the outriggers can be manually or automatically inserted into the layout file after the locations of the attenuating features have been determined. The outriggers are not patterned on the substrate, but assist in forming resist features of uniform width.
摘要翻译：一种用于设计和形成掩模版（40）的方法以及使用该掩模版（40）制造半导体衬底（50）。本发明在密集和半致密特征图案中的特征（30）之间放置支架（32,34,36），以有助于图案化装置特征。外悬支架的宽度可以基于半密集或密集特征图案中的特征之间的间距和位置来改变。在一个实施例中，在已经确定衰减特征的位置之后，外伸支架可以手动地或自动地插入到布局文件中。外延支架不在基板上图案化，但有助于形成均匀宽度的抗蚀剂特征。

8. 发明申请

US20090130865A1 METHOD OF PATTERNING A LAYER USING A PELLICLE 有权
标题翻译：使用细胞膜分层的方法
公开(公告)号：US20090130865A1
公开(公告)日：2009-05-21
申请号：US12279672
申请日：2006-02-17
申请人： Kevin Lucas , Kyle Patterson , Sergei Postnikov
发明人： Kevin Lucas , Kyle Patterson , Sergei Postnikov
IPC分类号： H01L21/428
CPC分类号： G03F1/62 , G03F1/36
摘要： A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.
摘要翻译：用于在半导体衬底上图案化层的方法包括形成半导体衬底的层并将该层暴露于光。光穿过通过包括确定通过第一防护薄膜的第一光的第一透射的方法制造的第二防护薄膜，其中第一光垂直于第一防护薄膜，确定通过第一防护膜的第二光的第二透射防护薄膜，其中所述第二光不与所述第一防护薄膜正交，并且使用所述第一和第二透射来修饰所述第一防护薄膜以形成第二防护薄膜。

9. 发明申请

US20060199087A1 Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure field 审中-公开
标题翻译：通过考虑基于曝光区域内的位置而变化的参数来修改设计布局来制作集成电路的方法
公开(公告)号：US20060199087A1
公开(公告)日：2006-09-07
申请号：US11071809
申请日：2005-03-03
申请人： Kevin Lucas , Robert Boone , Kyle Patterson
发明人： Kevin Lucas , Robert Boone , Kyle Patterson
IPC分类号： G03F7/00
CPC分类号： G03F7/70441 , G03F7/70941
摘要： An original layout of an integrated circuit is modified using optical proximity correction (OPC) to obtain a second layout. During OPC, a sensitivity to flare for each feature is conveniently identified. To map the flare, the amplitude of intensity is mapped over a field of exposure, which is typically a rectangle-shaped area corresponding to an exposure of a stepper. The field of exposure is divided into regions in which a region is characterized as having substantially the same amplitude throughout. For each feature a decision is made whether to make a further correction or not. If correction is desired, the amount of correction is based in part on the region in which the feature is located and the sensitivity of the feature. This same approach is applicable to other properties than flare that vary based on the location within the field of exposure.
摘要翻译：使用光学邻近校正（OPC）修改集成电路的原始布局以获得第二布局。在OPC期间，可以方便地识别每个功能对闪光的敏感度。为了映射耀斑，将强度的幅度映射在曝光场上，该场通常是对应于步进曝光的矩形区域。曝光领域被划分为其中区域被表征为具有基本上相同振幅的区域。对于每个功能，决定是否进一步修正。如果需要校正，校正量部分地基于特征所在的区域和特征的灵敏度。这种相同的方法适用于根据暴露领域内的位置而变化的其他特性。

10. 发明授权

US06174810B1 Copper interconnect structure and method of formation 失效
标题翻译：铜互连结构和形成方法
公开(公告)号：US06174810B1
公开(公告)日：2001-01-16
申请号：US09055510
申请日：1998-04-06
申请人： Rabiul Islam , Avgerinos V. Gelatos , Kevin Lucas , Stanley M. Filipiak , Ramnath Venkatraman
发明人： Rabiul Islam , Avgerinos V. Gelatos , Kevin Lucas , Stanley M. Filipiak , Ramnath Venkatraman
IPC分类号： H01L2144
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76838
摘要： In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form interconnect openings (29). A layer of copper (34) is then formed within the interconnect openings (29). A portion of the copper layer (34) is then removed to form copper interconnects (39) within the interconnect openings (29). A copper barrier layer (40) is then formed overlying the copper interconnects (39). Adhesion between the copper barrier layer (40) and the copper interconnects (39) is improved by exposing the exposed surface of the copper interconnects (39) to a plasma generated using only ammonia as a source gas.
摘要翻译：在一个实施例中，通过在半导体衬底（10）上沉积介电层（28）来形成铜互连结构。然后将电介质层（28）图案化以形成互连开口（29）。然后在互连开口（29）内形成一层铜（34）。然后去除铜层（34）的一部分以在互连开口（29）内形成铜互连（39）。然后在铜互连（39）上形成铜阻挡层（40）。通过将铜互连（39）的暴露表面暴露于仅使用氨作为源气体产生的等离子体，可以改善铜阻挡层（40）和铜互连（39）之间的粘合性。

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