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1. 发明授权

US5682394A Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
标题翻译：容错计算机存储器系统和采用双级错误校正和检测功能的组件
公开(公告)号：US5682394A
公开(公告)日：1997-10-28
申请号：US012186
申请日：1993-02-02
申请人： Robert Martin Blake , Douglas Craig Bossen , Chin-Long Chen , John Atkinson Fifield , Howard Leo Kalter
发明人： Robert Martin Blake , Douglas Craig Bossen , Chin-Long Chen , John Atkinson Fifield , Howard Leo Kalter
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which is tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
摘要翻译：在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正的机制来增强存储器的可靠性能力，例如，响应于在一个存储器单元中发生不可校正的错误。这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

2. 发明授权

US6034389A Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中的深沟槽电容器的自对准扩散源垂直晶体管
公开(公告)号：US6034389A
公开(公告)日：2000-03-07
申请号：US792952
申请日：1997-01-22
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
IPC分类号： H01L21/8247 , H01L21/24 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10841 , Y10S257/906 , Y10S257/908
摘要： A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of all the cells are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的具有柱状和深沟槽电容器的垂直半导体器件阵列及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。所有细胞的较低掺杂区彼此分离，而不增加细胞大小，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为深沟槽电容器不增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底隔离的浮动柱，或者保持柱和衬底之间的接触。

3. 发明授权

US6077745A Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中堆叠电容器的自对准扩散源垂直晶体管
公开(公告)号：US6077745A
公开(公告)日：2000-06-20
申请号：US960250
申请日：1997-10-29
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/115 , H01L27/11517 , H01L27/10852
摘要： A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4 F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的垂直半导体器件阵列，其上具有堆叠电容器的柱及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。相邻位线的较低掺杂区域可以彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为堆叠电容器不会增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底分离的浮动柱，或者保持柱和衬底之间的接触。

4. 发明授权

US5929477A Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中堆叠电容器的自对准扩散源垂直晶体管
公开(公告)号：US5929477A
公开(公告)日：1999-07-27
申请号：US792955
申请日：1997-01-22
申请人： Stuart McAllister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
发明人： Stuart McAllister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/108 , H01L29/76
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/115 , H01L27/11517 , H01L27/10852
摘要： A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的垂直半导体器件阵列，其上具有堆叠电容器的柱及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。相邻位线的较低掺杂区域可以彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为堆叠电容器不会增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底分离的浮动柱，或者保持柱和衬底之间的接触。

5. 发明授权

US5866443A Very dense integrated circuit package and method for forming the same 失效
标题翻译：非常密集的集成电路封装及其形成方法
公开(公告)号：US5866443A
公开(公告)日：1999-02-02
申请号：US884074
申请日：1997-06-27
申请人： H. Bernhard Pogge , Johann Greschner , Howard Leo Kalter , Raymond James Rosner
发明人： H. Bernhard Pogge , Johann Greschner , Howard Leo Kalter , Raymond James Rosner
IPC分类号： H01L21/28 , H01L21/301 , H01L21/98 , H01L25/065 , H01L29/06 , H01L21/44
CPC分类号： H01L25/50 , H01L25/0655 , H01L29/0657 , H01L2924/0002
摘要： Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.
摘要翻译：公开了一种集成电路结构，其包括具有用于支撑各个半导体管芯单元的凹部的载体。半导体管芯单元和载体凹槽具有光刻定义的尺寸，以便能够精确对准和高集成度。

6. 发明授权

US5663924A Boundary independent bit decode for a SDRAM 失效
标题翻译：用于SDRAM的边界独立位解码
公开(公告)号：US5663924A
公开(公告)日：1997-09-02
申请号：US572604
申请日：1995-12-14
申请人： John Edward Barth, Jr. , Howard Leo Kalter
发明人： John Edward Barth, Jr. , Howard Leo Kalter
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1018
摘要： A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address is decoded by an SDRAM column decoder. The decoder selects a starting boundary for 2n bits. The first requested bit is in the first n bits of the 2n selected bits. Thus, the entire n bit block is included in the selected 2n bit block. The n bit block is selected from the selected 2n bits and latched in a high speed decoder/register in a sequentially scrambled order, i.e., the i.sup.th bit is the first requested bit and the requested bit order is i, . . . , (n-1), . . . , 0, . . . , (i-1). Latched data is scrambled either sequentially or interleaved, if required. Scrambled data is burst transferred off chip.
摘要翻译：具有n位突发传输块长度的同步动态随机存取存储器（SDRAM）的边界独立解码器。用户，通常是处理器或微处理器请求访问一块SDRAM存储器。所请求的块可以在阵列解码边界之间开始。列地址由SDRAM列解码器解码。解码器为2n位选择起始边界。第一个请求位在2n个选定位的前n位。因此，整个n位块被包括在所选择的2n位块中。从选定的2n位中选择n位块，并以顺序加扰的顺序锁存在高速解码器/寄存器中，即第i个位是第一个请求位，并且所请求的位顺序为i。。。，（n-1），。。。，0，。。。，（i-1）。如果需要，锁存数据按顺序或交错进行加扰。加扰数据是芯片外的突发传输。

7. 发明授权

US5656544A Process for forming a polysilicon electrode in a trench 失效
标题翻译：在沟槽中形成多晶硅电极的工艺
公开(公告)号：US5656544A
公开(公告)日：1997-08-12
申请号：US391904
申请日：1995-02-21
申请人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
发明人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
IPC分类号： H01L27/10 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/44 , H01L21/48
CPC分类号： H01L29/7882 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/115
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译：公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。本发明的阵列提供高密度影子RAM。还公开了用于制造本发明的装置的方法。

8. 发明授权

US6137128A Self-isolated and self-aligned 4F-square vertical fet-trench dram cells 失效
标题翻译：自分离和自对准4F方形垂直胎面沟槽细胞
公开(公告)号：US6137128A
公开(公告)日：2000-10-24
申请号：US94383
申请日：1998-06-09
申请人： Steven John Holmes , Howard Leo Kalter , Sandip Tiwari , Jeffrey John Welser
发明人： Steven John Holmes , Howard Leo Kalter , Sandip Tiwari , Jeffrey John Welser
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10864 , H01L29/945 , H01L27/10823 , H01L27/1087
摘要： A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor channels, and may be formed utilizing the application of hybrid resist over a block of semiconductor material. Drain doped regions are formed on the top of each pillar. The source doped regions and the plate doped regions are self-aligned and are created by diffusion in the trenches surrounding the pillars. The array has columns of bitlines and rows of wordlines. The capacitors are formed by isolating n.sup.+ polysilicon in trenches separating said pillars. The array is suitable for GBit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline architecture, where the plate region is common to all the storage nodes or a folded architecture with two wordlines that pass through each cell having stacked transistors, where one wordline is active and the other is passing for each cell.
摘要翻译：公开了一种密集堆叠的垂直半导体器件阵列，具有支柱，深沟槽电容器，垂直晶体管及其制造方法。支柱用作晶体管通道，并且可以利用在半导体材料块上施加混合抗蚀剂来形成。在每个支柱的顶部形成漏极掺杂区域。源掺杂区域和板掺杂区域是自对准的，并且通过在柱子周围的沟槽中的扩散而产生。该阵列具有位线和字线行。通过在分离所述柱的沟槽中隔离n +多晶硅来形成电容器。该阵列适用于GBit DRAM应用，因为深沟槽电容器不增加阵列面积。阵列可以具有开放的位线架构，其中板区域对于所有存储节点是公共的，或者具有两个字线的折叠结构，其中两个字线通过具有堆叠晶体管的每个单元，其中一个字线是活动的，而另一个字线通过每个单元。

9. 发明授权

US5961653A Processor based BIST for an embedded memory 失效
标题翻译：基于处理器的BIST，用于嵌入式存储器
公开(公告)号：US5961653A
公开(公告)日：1999-10-05
申请号：US803053
申请日：1997-02-19
申请人： Howard Leo Kalter , John Edward Barth, Jr. , Jeffrey Harris Dreibelbis , Rex Ngo Kho , John Stuart Parenteau, Jr. , Donald Lawrence Wheater , Yotaro Mori
发明人： Howard Leo Kalter , John Edward Barth, Jr. , Jeffrey Harris Dreibelbis , Rex Ngo Kho , John Stuart Parenteau, Jr. , Donald Lawrence Wheater , Yotaro Mori
IPC分类号： G01R31/28 , G06F11/273 , G11C29/02 , G11C29/12 , G11C29/32 , G06F11/00
CPC分类号： G06F11/2635 , G11C29/12 , G11C29/32
摘要： An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.
摘要翻译：具有嵌入在逻辑中的DRAM的集成芯片通过原位处理器定向的BIST宏进行测试。 BIST提供两个ROMS，一个用于存储测试指令，另一个用于存储测试指令，第二个可扫描，为存储在第一个ROM中的测试指令提供顺序，以及分支和循环功能。此外，BIST宏还具有用于监视DRAM内的故障并用于替换失败的字和/或数据线的冗余分配逻辑部分。通过将DRAM以0.5mb的增量叠加到4.0mb的最大值或以1.0mb的增量最大为8mb的最大值，所有这些都由BIST宏控制和测试，具有高度粒度的定制芯片设计可以是实现并针对更大的ASIC中的特定应用量身定做。

10. 发明授权

US5796662A Integrated circuit chip with a wide I/O memory array and redundant data lines 失效
标题翻译：具有宽I / O存储器阵列和冗余数据线的集成电路芯片
公开(公告)号：US5796662A
公开(公告)日：1998-08-18
申请号：US756614
申请日：1996-11-26
申请人： Howard Leo Kalter , John Edward Barth, Jr.
发明人： Howard Leo Kalter , John Edward Barth, Jr.
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/848
摘要： An integrated circuit chip with RAM, a RAM macro or bit slice data logic and at least one spare array element or spare slice element and the redundancy scheme therefor. The chip includes a wide data path with a plurality of interchangeable elements such as bit slice elements or memory element and at least one more element than the number of bits in the wide data path; selection logic for deselecting defective data elements; and, switches for selectively coupling each bit of the wide I/O data path to one element or to an element adjacent the one element responsive to the selection means. The integrated circuit chip may further include drive means for selectively driving data from the switches to the element or, otherwise, passing data from the elements to the switches. The switches preferably are three-way switches, such as three CMOS pass gates.
摘要翻译：具有RAM的集成电路芯片，RAM宏或位片数据逻辑以及至少一个备用阵列元件或备用片元件及其冗余方案。芯片包括具有诸如位片元件或存储器元件的多个可互换元件的宽数据路径以及与宽数据路径中的位数比至少一个元素; 用于取消选择有缺陷的数据元素的选择逻辑; 以及用于响应于选择装置选择性地将宽I / O数据路径的每一位耦合到一个元件或与该元件相邻的元件的开关。集成电路芯片还可以包括用于选择性地将数据从开关驱动到元件的驱动装置，或者否则将数据从元件传递到开关。开关优选地是三路开关，例如三个CMOS通孔。

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