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1. 发明授权

US5656544A Process for forming a polysilicon electrode in a trench 失效
标题翻译：在沟槽中形成多晶硅电极的工艺
公开(公告)号：US5656544A
公开(公告)日：1997-08-12
申请号：US391904
申请日：1995-02-21
申请人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
发明人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
IPC分类号： H01L27/10 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/44 , H01L21/48
CPC分类号： H01L29/7882 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/115
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译：公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。本发明的阵列提供高密度影子RAM。还公开了用于制造本发明的装置的方法。

2. 发明授权

US5691549A Sidewall strap 失效
标题翻译：侧壁带
公开(公告)号：US5691549A
公开(公告)日：1997-11-25
申请号：US720991
申请日：1996-10-15
申请人： Chung Hon Lam , James S. Nakos , Donald McAlpine Kenney , Eric Adler
发明人： Chung Hon Lam , James S. Nakos , Donald McAlpine Kenney , Eric Adler
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/485 , H01L29/80 , H01L31/112
CPC分类号： H01L27/10861 , H01L21/76897 , H01L23/485 , H01L2924/0002 , Y10S257/90
摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.
摘要翻译：本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。侧壁连接器具有包括表面的顶部部分。导电构件接触顶部，将轨道连接到导电区域或外部导体。位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。连接器用于形成用于DRAM单元的带子。

3. 发明授权

US08445313B2 Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 失效
标题翻译：用于形成PCRAM和自对准回蚀工艺的自对准位线的方法
公开(公告)号：US08445313B2
公开(公告)日：2013-05-21
申请号：US13546684
申请日：2012-07-11
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

4. 发明申请

US20120202333A1 METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS 有权
标题翻译：用于形成用于PCRAM和自对准回退过程的自对准位线的方法
公开(公告)号：US20120202333A1
公开(公告)日：2012-08-09
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/02
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，其包括在下电极的一部分上形成牺牲材料的基座并且与邻近所述牺牲材料的至少一个电介质材料相连，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

5. 发明授权

US08238149B2 Methods and apparatus for reducing defect bits in phase change memory 有权
标题翻译：用于减少相变存储器中缺陷位的方法和装置
公开(公告)号：US08238149B2
公开(公告)日：2012-08-07
申请号：US12715802
申请日：2010-03-02
申请人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

6. 发明申请

US20120193599A1 PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING 有权
标题翻译：相变式存储单元阵列与自适应底层电极及其制造方法
公开(公告)号：US20120193599A1
公开(公告)日：2012-08-02
申请号：US13445194
申请日：2012-04-12
申请人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。最后，在存储器元件上形成位线以完成存储器单元。在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

7. 发明授权

US08138574B2 PCM with poly-emitter BJT access devices 有权
标题翻译： PCM与多发射器BJT接入设备
公开(公告)号：US08138574B2
公开(公告)日：2012-03-20
申请号：US12510588
申请日：2009-07-28
申请人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
发明人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
IPC分类号： H01L27/06
CPC分类号： H01L45/1233 , H01L27/2445 , H01L27/2463 , H01L45/06
摘要： A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.
摘要翻译：相变存储器（PCM）包括包括多个存储器单元的阵列，包括相变元件（PCE）的存储单元; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。用于相变存储器（PCM）的存储单元包括相变元件（PCE）; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。

8. 发明授权

US08055988B2 Multi-bit memory error detection and correction system and method 有权
标题翻译：多位存储器错误检测和校正系统及方法
公开(公告)号：US08055988B2
公开(公告)日：2011-11-08
申请号：US11694025
申请日：2007-03-30
申请人： Chung Hon Lam
发明人： Chung Hon Lam
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1072 , G11C11/56 , G11C11/5621 , G11C11/5678 , G11C13/0004 , G11C27/005 , G11C29/00 , G11C2211/5641
摘要： A system and method for operating a collection of memory cells includes storing binary data values and parity data values by associating binary values with a common adjustable characteristic parameter of a memory cell collection. Probability distribution functions for values of the characteristic parameter of the memory cell collection are read and constructed. Binary data values and parity data values stored in the memory cell collection are retrieved. Parity data for error detection and error correction is evaluated in the binary data values.
摘要翻译：用于操作存储器单元的集合的系统和方法包括通过将二进制值与存储器单元集合的公共可调特性参数相关联来存储二进制数据值和奇偶校验数据值。对存储单元集合的特性参数的值的概率分布函数进行读取和构造。检索存储在存储单元集合中的二进制数据值和奇偶校验数据值。用于错误检测和纠错的奇偶校验数据在二进制数据值中进行评估。

9. 发明申请

US20110207286A1 Reprogrammable Fuse Structure and Method 有权
标题翻译：可编程保险丝结构与方法
公开(公告)号：US20110207286A1
公开(公告)日：2011-08-25
申请号：US13100456
申请日：2011-05-04
申请人： Geoffrey W. Burr , Chandrasekharan Kothandaraman , Chung Hon Lam , Xiao Hu Liu , Stephen M. Rossnagel , Christy S. Tyberg , Robert L. Wisnieff
发明人： Geoffrey W. Burr , Chandrasekharan Kothandaraman , Chung Hon Lam , Xiao Hu Liu , Stephen M. Rossnagel , Christy S. Tyberg , Robert L. Wisnieff
IPC分类号： H01L21/768
CPC分类号： H01L23/5256 , H01L23/5252 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1683 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.
摘要翻译：集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。

10. 发明授权

US07932507B2 Current constricting phase change memory element structure 有权
标题翻译：电流限制相变存储元件结构
公开(公告)号：US07932507B2
公开(公告)日：2011-04-26
申请号：US12727672
申请日：2010-03-19
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L29/02
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

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