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1. 发明授权

US07951660B2 Methods for fabricating a metal-oxide-semiconductor device structure 有权
标题翻译：金属氧化物半导体器件结构的制造方法
公开(公告)号：US07951660B2
公开(公告)日：2011-05-31
申请号：US10703355
申请日：2003-11-07
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Larry Alan Nesbit
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/2807 , H01L29/4908
摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.
摘要翻译：一种制造金属氧化物半导体器件结构的方法。该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影栅电极中的掺杂物种类的范围位于栅电极内。结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

2. 发明授权

US07923202B2 Layer patterning using double exposure processes in a single photoresist layer 有权
标题翻译：在单一光致抗蚀剂层中使用双曝光工艺的层图案化
公开(公告)号：US07923202B2
公开(公告)日：2011-04-12
申请号：US11831099
申请日：2007-07-31
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： G03F7/26
CPC分类号： G03F7/2024 , G03F7/38 , G03F7/40 , G03F7/70425
摘要： A structure and a method for forming the same. The method includes providing a structure which includes (a) a to-be-patterned layer, (b) a photoresist layer on top of the to-be-patterned layer wherein the photoresist layer includes a first opening, and (c) a cap region on side walls of the first opening. A first top surface of the to-be-patterned layer is exposed to a surrounding ambient through the first opening. The method further includes performing a first lithography process resulting in a second opening in the photoresist layer. The second opening is different from the first opening. A second top surface of the to-be-patterned layer is exposed to a surrounding ambient through the second opening.
摘要翻译：一种结构及其形成方法。该方法包括提供一种结构，其包括（a）待图案化层，（b）在待图案化层的顶部上的光致抗蚀剂层，其中光致抗蚀剂层包括第一开口，和（c）帽区域在第一开口的侧壁上。待图案化层的第一顶表面通过第一开口暴露于周围环境。该方法还包括执行在光致抗蚀剂层中产生第二开口的第一光刻工艺。第二个开口与第一个开口不同。待图案化层的第二顶表面通过第二开口暴露于周围环境。

3. 发明授权

US07820502B2 Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby 有权
标题翻译：制造垂直碳纳米管场效应晶体管的方法，用于排列阵列和由此形成的场效应晶体管和阵列
公开(公告)号：US07820502B2
公开(公告)日：2010-10-26
申请号：US11926627
申请日：2007-10-29
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaolav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaolav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： H01L21/8238
CPC分类号： H01L51/057 , B82Y10/00 , G11C13/025 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/66409 , H01L29/772 , H01L51/0048 , Y10S977/734
摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.
摘要翻译：一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。多个器件结构可以被配置为存储器电路或逻辑电路。

4. 发明授权

US07691720B2 Vertical nanotube semiconductor device structures and methods of forming the same 有权
标题翻译：垂直纳米管半导体器件结构及其形成方法
公开(公告)号：US07691720B2
公开(公告)日：2010-04-06
申请号：US11926661
申请日：2007-10-29
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： H01L21/76
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10S977/70 , Y10S977/734 , Y10S977/742
摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.
摘要翻译：结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

5. 发明授权

US07607455B2 Micro-electro-mechanical valves and pumps and methods of fabricating same 有权
标题翻译：微机电阀和泵及其制造方法
公开(公告)号：US07607455B2
公开(公告)日：2009-10-27
申请号：US12127975
申请日：2008-05-28
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： F16K31/02 , F04B17/00
CPC分类号： F15C1/06 , F04B43/043 , F15C5/00 , F16K99/0001 , F16K99/0015 , F16K99/0051 , F16K2099/0074 , F16K2099/0094 , Y10T29/49236 , Y10T29/49412 , Y10T137/2224
摘要： Micro-valves and micro-pumps and methods of fabricating micro-valves and micro-pumps. The micro-valves and micro-pumps include electrically conductive diaphragms fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves and pumping action of the micro-pumps is accomplished by applying electrostatic forces to the electrically conductive diaphragms.
摘要翻译：微型阀门和微型泵以及制造微型阀门和微型泵的方法。微型阀和微型泵包括由导电纳米纤维制成的导电隔膜。通过微型阀的流体流动和微型泵的泵送作用是通过将静电力施加到导电隔膜来实现的。

6. 发明申请

US20080258222A1 Design Structure Incorporating a Hybrid Substrate 失效
标题翻译：混合基板的设计结构
公开(公告)号：US20080258222A1
公开(公告)日：2008-10-23
申请号：US11877871
申请日：2007-10-24
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Jack Allan Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L27/12
CPC分类号： H01L21/76264
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
摘要翻译：设计结构体现在机器可读介质中，用于设计，制造或测试设计，其中设计结构包括以混合衬底形成的器件，其特征在于具有不同晶体取向的半导体岛。绝缘层将至少一个不同晶体取向的岛分成相互排列的器件和体区。身体区域可以相对于装置区域电浮动。

7. 发明申请

US20080197448A1 SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 审中-公开
标题翻译：通过SiO 2的液相沉积沉积分离膜
公开(公告)号：US20080197448A1
公开(公告)日：2008-08-21
申请号：US12112549
申请日：2008-04-30
申请人： Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Peter H. Mitchell , Larry Alan Nesbit
发明人： Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84
摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.
摘要翻译：为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区与氧化物。通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其他氧化物区域。

8. 发明授权

US07329567B2 Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage 失效
标题翻译：掺杂半导体纳米管的垂直场效应晶体管在间隔物界定的通道中生长
公开(公告)号：US07329567B2
公开(公告)日：2008-02-12
申请号：US11180415
申请日：2005-07-13
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L27/283 , B82Y10/00 , H01L51/0048 , H01L51/057 , Y10S977/70 , Y10S977/707 , Y10S977/721 , Y10S977/724
摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
摘要翻译：具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。可以在远离通道的口的间隔件的基部中设置间隙。通过间隙流过催化剂垫的反应物参与纳米管生长。

9. 发明授权

US07211844B2 Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage 有权
标题翻译：掺杂半导体纳米管的垂直场效应晶体管在间隔物界定的通道中生长
公开(公告)号：US07211844B2
公开(公告)日：2007-05-01
申请号：US10767039
申请日：2004-01-29
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： H01L29/76
CPC分类号： H01L27/283 , B82Y10/00 , H01L51/0048 , H01L51/057 , Y10S977/70 , Y10S977/707 , Y10S977/721 , Y10S977/724
摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
摘要翻译：具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。可以在远离通道的口的间隔件的基部中设置间隙。通过间隙流过催化剂垫的反应物参与纳米管生长。

10. 发明授权

US06015750A Method for improving visibility of alignment target in semiconductor processing 失效
标题翻译：用于提高半导体处理中的对准目标的可见性的方法
公开(公告)号：US06015750A
公开(公告)日：2000-01-18
申请号：US7694
申请日：1998-01-15
申请人： James A. Bruce , Steven John Holmes , Robert K. Leidy
发明人： James A. Bruce , Steven John Holmes , Robert K. Leidy
IPC分类号： H01L23/544 , G01B11/27
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
摘要翻译：公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。根据第一实施例，在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。根据第二实施例，在金属层上添加反射涂层以增强金属层的反射率。根据第三实施例，在整个晶片上添加反射涂层以增强金属层的反射率。根据第四实施例，添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。根据第五实施例，添加有机抗反射涂层以降低邻近对准靶的材料的反射率。所有这些实施例导致对准目标和相邻材料之间的对比度，其与氧化物厚度的变化更一致。更均匀的对比度使得步进系统更容易识别对准目标的边缘，导致掩模更准确的放置。

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