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1. 发明授权

US07203126B2 Integrated circuit systems and devices having high precision digital delay lines therein 失效
标题翻译：其中具有高精度数字延迟线的集成电路系统和装置
公开(公告)号：US07203126B2
公开(公告)日：2007-04-10
申请号：US11134899
申请日：2005-05-23
申请人： Robert J. Proebsting , Cesar A. Talledo , David J. Pilling
发明人： Robert J. Proebsting , Cesar A. Talledo , David J. Pilling
IPC分类号： G11C8/18
CPC分类号： H03H11/265 , H03K3/0322 , H03K5/133 , H03K5/135 , H03K2005/00032 , H03K2005/00104 , H03K2005/00208 , H03K2005/00247 , H03K2005/00286 , H03L7/0812
摘要： An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.
摘要翻译：集成电路延迟装置包括数字延迟线，其被配置为响应于控制信号向在其输入处接收的定时信号提供百分比时钟周期延迟。该控制信号具有指定延迟长度的值。还提供延迟线控制电路。延迟线控制电路被配置为通过在具有大于时钟周期的持续时间的时间间隔内对具有小于时钟周期的周期的高频振荡器信号（例如，环形振荡器信号）的多个周期进行计数来生成控制信号。

2. 发明授权

US06944070B1 Integrated circuit devices having high precision digital delay lines therein 有权
标题翻译：具有高精度数字延迟线的集成电路器件
公开(公告)号：US06944070B1
公开(公告)日：2005-09-13
申请号：US10880893
申请日：2004-06-30
申请人： Robert J. Proebsting , Cesar A. Talledo , David J. Pilling
发明人： Robert J. Proebsting , Cesar A. Talledo , David J. Pilling
IPC分类号： G11C7/00 , H03H11/26 , H03K3/03 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/081
CPC分类号： H03H11/265 , H03K3/0322 , H03K5/133 , H03K5/135 , H03K2005/00032 , H03K2005/00104 , H03K2005/00208 , H03K2005/00247 , H03K2005/00286 , H03L7/0812
摘要： Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period. The ring oscillator signal may be generated by a ring oscillator having a relatively small number of stages and the time interval may be sufficiently long so that a large number of cycles of the ring oscillator signal may be counted over many periods of the clock signal.
摘要翻译：集成电路延迟装置包括数字延迟线，其被配置为向在其多个注入端口中的启用的一个注入端口处接受的定时信号提供百分比时钟周期延迟。数字延迟线可以响应于具有通过指定多个注入端口中的启用的一个的注入端口的位置来设置延迟的长度的值的注入控制信号，延迟线的末端是固定的输出端口。还提供延迟线控制电路，其响应于具有优选地测量百分比时钟周期延迟的周期的时钟信号。延迟线控制电路被配置为通过在具有持续时间大于的时间间隔的周期小于并且通常基本上小于时钟周期的周期来计数高频环形振荡器信号的多个周期来产生注入控制信号，并且通常基本上大于时钟周期。环形振荡器信号可以由具有相对较少级数的环形振荡器产生，并且时间间隔可能足够长，使得环形振荡器信号的大量周期可以在时钟信号的多个周期上被计数。

3. 发明授权

US06856558B1 Integrated circuit devices having high precision digital delay lines therein 有权
公开(公告)号：US06856558B1
公开(公告)日：2005-02-15
申请号：US10643208
申请日：2003-08-18
申请人： Robert J. Proebsting , Cesar A. Talledo , David J. Pilling
发明人： Robert J. Proebsting , Cesar A. Talledo , David J. Pilling
IPC分类号： G11C7/00 , H03H11/26 , H03K3/03 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/081
CPC分类号： H03H11/265 , H03K3/0322 , H03K5/133 , H03K5/135 , H03K2005/00032 , H03K2005/00104 , H03K2005/00208 , H03K2005/00247 , H03K2005/00286 , H03L7/0812
摘要： Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period. The ring oscillator signal may be generated by a ring oscillator having a relatively small number of stages and the time interval may be sufficiently long so that a large number of cycles of the ring oscillator signal may be counted over many periods of the clock signal.

4. 发明授权

US08041552B2 Behavioral modeling of high speed differential signals based on physical characteristics 有权
标题翻译：基于物理特性的高速差分信号的行为建模
公开(公告)号：US08041552B2
公开(公告)日：2011-10-18
申请号：US11786175
申请日：2007-04-10
申请人： David J. Pilling
发明人： David J. Pilling
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizing that parameter is constructed. The behavioral model can then be utilized to predict the behavior of the integrated circuit output drivers.
摘要翻译：提供了一种对集成电路中的输出驱动器进行建模的方法，例如串行器/解串器电路。根据本发明的实施例，物理地测量电路的至少一个参数，并构建利用该参数的行为模型。然后可以利用行为模型来预测集成电路输出驱动器的行为。

5. 发明授权

US5838624A Circuits for improving the reliability of antifuses in integrated circuits 失效
标题翻译：用于提高集成电路中反熔丝可靠性的电路
公开(公告)号：US5838624A
公开(公告)日：1998-11-17
申请号：US850902
申请日：1997-05-02
申请人： David J. Pilling , Raymond M. Chu , Sik K. Lui
发明人： David J. Pilling , Raymond M. Chu , Sik K. Lui
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18
摘要： A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish this, an antifuse has applied across its two terminals a "reading" or "evaluation" voltage as required by the system operation for a single read or evaluation clock period (typically 5 ns to 30 ns in duration). The signal describing the state of the antifuse is then stored in a latch, register, or other suitable structure for subsequent sampling. In this manner, a low read current flows in the antifuse in response to the standard chip operating voltage for only a short period of time such as a single clock cycle. Thus, continuous voltages across the two terminals of the antifuse are avoided and an unprogrammed antifuse is not inadvertently programmed and a programmed antifuse is not inadvertently converted back to its high impedance state (i.e. "unprogrammed"). In another embodiment, a multiplexer coupled to a terminal of the antifuse switches the terminal of the antifuse to a programming voltage node when the antifuse is selected for programming and to a reference voltage source when the antifuse is not selected for programming. The multiplexer prevents undesired voltages from being applied across the antifuse while other antifuses are being programmed. The two embodiments discussed may be used in conjunction with each other or separately.
摘要翻译：电路通过基本消除反熔丝端子上的电压的连续不期望的应用来提高某些类型系统中反熔丝的可靠性。为了实现这一点，反熔丝在其两个端子上施加了对于单个读取或评估时钟周期（通常为5ns至30ns的持续时间）的系统操作所需的“读取”或“评估”电压。然后将描述反熔丝的状态的信号存储在锁存器，寄存器或其他合适的结构中，用于随后的采样。以这种方式，仅在短时间段（例如单个时钟周期）内，低反向电流响应于标准芯片工作电压而流过反熔丝。因此，避免了反熔丝两端的连续电压，并且不会无意地编程未编程的反熔丝，并且编程的反熔丝不会无意中转换回其高阻抗状态（即“未编程”）。在另一个实施例中，当反熔丝被选择用于编程时，耦合到反熔丝的端子的多路复用器将反熔丝的端子切换到编程电压节点，并且当反熔丝未被选择用于编程时，将其转换为参考电压源。多路复用器防止在反熔丝跨越反熔丝而施加不需要的电压，而其他反熔丝被编程。所讨论的两个实施例可以彼此结合使用或分开使用。

6. 发明授权

US5677888A Redundancy circuit for programmable integrated circuits 失效
标题翻译：可编程集成电路冗余电路
公开(公告)号：US5677888A
公开(公告)日：1997-10-14
申请号：US473041
申请日：1995-06-06
申请人： Sik K. Lui , Raymond M. Chu , David J. Pilling
发明人： Sik K. Lui , Raymond M. Chu , David J. Pilling
IPC分类号： G06F11/00 , G11C17/16 , G11C17/18 , G11C29/00
CPC分类号： G11C29/781 , G06F11/00 , G11C17/16 , G11C17/18 , G11C29/785 , Y10S257/919
摘要： An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.
摘要翻译：反熔丝冗余电路对外部电路和用户具有透明度。在一个实施例中，反熔丝冗余电路包括两个反熔丝而不是一个。电路被布置成使得两个反熔丝可以被同时编程和读取。如果在不编写其他反熔丝的情况下对单个反熔丝进行编程，则反熔丝冗余电路将注册编程的反熔丝。此外，如果在冗余电路中的两个反熔丝编程之后，单个编程的反熔丝被无意地解除编程，则反熔丝冗余电路将继续注册编程的反熔丝。结果是制造产量的增加和利用反熔丝的集成电路的可靠性的增加。

7. 发明授权

US5608685A Adjacent row shift redundancy circuit having signal restorer coupled to programmable links and a method thereof 失效
标题翻译：具有耦合到可编程链路的信号恢复器的相邻行移位冗余电路及其方法
公开(公告)号：US5608685A
公开(公告)日：1997-03-04
申请号：US451708
申请日：1995-05-26
申请人： Larry D. Johnson , David J. Pilling
发明人： Larry D. Johnson , David J. Pilling
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/787
摘要： A redundancy circuit for a semiconductor memory device utilizes a fuse ladder comprising alternating programmable resistive fuses and signal restorers connected to one another in series. The signal restorers coupled between the fuses prevent the formation of a high impedance resistive line with a floating node when one of the fuses in the ladder is blown.
摘要翻译：用于半导体存储器件的冗余电路利用包括交替可编程电阻熔丝和信号恢复器的熔丝梯，所述可编程电阻熔丝和信号恢复器彼此串联连接。耦合在保险丝之间的信号恢复器防止当梯子中的一个保险丝熔断时形成具有浮动节点的高阻抗电阻线。

8. 发明授权

US5325335A Memories and amplifiers suitable for low voltage power supplies 失效
标题翻译：适用于低压电源的存储器和放大器
公开(公告)号：US5325335A
公开(公告)日：1994-06-28
申请号：US894414
申请日：1992-06-05
申请人： Michael A. Ang , David J. Pilling
发明人： Michael A. Ang , David J. Pilling
IPC分类号： G11C7/06 , G11C11/419 , G11C11/40
CPC分类号： G11C7/065 , G11C11/419
摘要： A sense amplifier for a static memory includes two pull-up transistors. The gate of each transistor is coupled to the drain of the other transistor. A circuitry is provided for precharging the drains of both pull-up transistors to a selected voltage such that by the start of the tracking stage of the amplifier, both pull-up transistors are off. If the tracking stage is long enough, one pull-up transistor turns on while the other one remains off, so that before the start of the sensing stage both pull-up transistors reach their final ON/OFF states. Hence the amplifier is fast and power efficient. The memory bit lines are precharged to VCC before the tracking stage, improving the read-disturb immunity and hence allowing a wider range of voltages on the bit lines and the sense amplifier inputs. The noise immunity and tolerance to temperature process variations are improved as a result. The high noise immunity make the amplifier and the memory suitable for integration with noisy circuits such as CPUs. High speed, high power efficiency, high noise immunity, high tolerance to temperature and process variations and high permissible range of bit line voltages make the memory and the amplifier suitable for low-voltage power supplies such as VCC=3.0 V supplies used in lap-top, notebook, sub-note book, and hand-held computers.
摘要翻译：用于静态存储器的读出放大器包括两个上拉晶体管。每个晶体管的栅极耦合到另一个晶体管的漏极。提供了一种用于将两个上拉晶体管的漏极预充电到所选电压的电路，使得通过放大器的跟踪级开始，两个上拉晶体管截止。如果跟踪阶段足够长，则一个上拉晶体管导通，而另一个上拉晶体管导通，因此在感测阶段开始之前，两个上拉晶体管都达到其最终的ON / OFF状态。因此，放大器是快速和功率效率。在跟踪阶段之前，存储器位线被预充电到VCC，从而提高读干扰抗扰度，从而允许位线和读出放大器输入端的电压范围更宽。结果，噪声抗扰度和对温度变化的耐受性得到改善。高抗噪性使放大器和存储器适合与诸如CPU之类的噪声电路集成。高速，高功率效率，高抗噪声能力，高耐温度和工艺变化以及高位允许范围的位线电压使存储器和放大器适用于低压电源，如VCC = 3.0 V电源，顶部，笔记本，子笔记本和手持电脑。

9. 发明申请

US20080204109A1 High-performance level shifter 有权
标题翻译：高性能电平转换器
公开(公告)号：US20080204109A1
公开(公告)日：2008-08-28
申请号：US11710371
申请日：2007-02-23
申请人： David J. Pilling , Mario Fulam Au
发明人： David J. Pilling , Mario Fulam Au
IPC分类号： H03L5/00
CPC分类号： H03K19/0013 , H03K19/01707 , H03K19/018521
摘要： A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching.
摘要翻译：提出了一种允许快速切换同时要求低功耗的电平转换器。根据本发明的一些实施例，电平移位器是双级电平移位电路，其中p沟道和n沟道晶体管被偏置，以便限制任何晶体管的源极到栅极或漏极之间的电势。上拉晶体管处于过渡状态，使得由增加或减小的输入电压引起的尖峰导通或关断上拉晶体管以辅助切换。

10. 发明授权

US06573775B2 Integrated circuit flip-flops that utilize master and slave latched sense amplifiers 失效
标题翻译：集成电路触发器，利用主和从锁存读出放大器
公开(公告)号：US06573775B2
公开(公告)日：2003-06-03
申请号：US10010847
申请日：2001-12-05
申请人： David J. Pilling
发明人： David J. Pilling
IPC分类号： H03K3289
CPC分类号： H03K3/356139 , H03K3/356191 , H03K5/00006
摘要： Flip-flops include a master stage and a slave stage. The master stage is responsive to a first clock signal and has a first pair of differential inputs and a first pair of differential outputs. The slave stage is responsive to a second clock signal and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs from which true and complementary outputs (Q, QB) of the flip-flop are derived. If the flip-flop is a D-type flip-flop, the first pair of differential inputs receive true and complementary data signals (DATA, DATAB). If the flip-flop is a set-reset (S-R) flip-flop, the first pair of differential inputs receive set and reset signals (SET, RESET).
摘要翻译：触发器包括主站和从站。主级响应于第一时钟信号并且具有第一对差分输入和第一对差分输出。从站级响应于第二时钟信号并且具有耦合到第一对差分输出的第二对差分输入和第二对差分输出，触发器的真实和互补输出（Q，QB）从该第二对差分输出派生。如果触发器是D型触发器，则第一对差分输入端接收真实和互补的数据信号（DATA，DATAB）。如果触发器是置位（S-R）触发器，则第一对差分输入端接收置位和复位信号（SET，RESET）。

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