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1. 发明申请

US20100095058A1 INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY 有权
标题翻译：集成电路随机存取存储器可自动内存刷新存储阵列
公开(公告)号：US20100095058A1
公开(公告)日：2010-04-15
申请号：US12635543
申请日：2009-12-10
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G06F12/00 , G11C7/00
CPC分类号： G11C11/40618 , G11C7/065 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/08 , G11C11/406 , G11C11/4076 , G11C11/4087 , G11C11/4091 , G11C2207/104 , G11C2207/229 , H01L27/10891 , H01L27/10897
摘要： A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.
摘要翻译：动态随机存取存储器集成电路和方法包括内部刷新控制和被配置为接收具有优先于待处理刷新请求的优先级的读和写访问请求的阵列，其中刷新请求可排队并且在不需要阵列访问并且完成的时钟周期上退休在一个时钟周期。不需要板载高速缓存。一种方法包括：当阵列中的一个阵列需要刷新时确定电路内的优先次序，优先考虑未决刷新请求的读取和写入访问请求，启动对阵列的访问的读取访问请求，而不确定数据是否可从数组外部获得，并且当该银行具有待处理的刷新请求并且不需要在该时钟周期上访问数组时，在一个时钟周期内退出一个等待刷新请求到银行。

2. 发明授权

US07640391B2 Integrated circuit random access memory capable of automatic internal refresh of memory array 有权
标题翻译：集成电路随机存取存储器能够自动内部刷新存储器阵列
公开(公告)号：US07640391B2
公开(公告)日：2009-12-29
申请号：US11085770
申请日：2005-03-21
申请人： Robert J Proebsting
发明人： Robert J Proebsting
IPC分类号： G06F12/00
CPC分类号： G11C11/40618 , G11C7/065 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/08 , G11C11/406 , G11C11/4076 , G11C11/4087 , G11C11/4091 , G11C2207/104 , G11C2207/229 , H01L27/10891 , H01L27/10897
摘要： A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.
摘要翻译：动态随机存取存储器集成电路和方法包括内部刷新控制和被配置为接收具有优先于待处理刷新请求的优先级的读和写访问请求的阵列，其中刷新请求可排队并且在不需要阵列访问并且完成的时钟周期上退休在一个时钟周期。不需要板载高速缓存。一种方法包括：当阵列中的一个阵列需要刷新时确定电路内的优先次序，优先考虑未决刷新请求的读取和写入访问请求，启动对阵列的访问的读取访问请求，而不确定数据是否可从数组外部获得，并且当该银行具有待处理的刷新请求并且不需要在该时钟周期上访问数组时，在一个时钟周期内退出一个等待刷新请求到银行。

3. 发明授权

US07092311B1 Content addressable memory (CAM) devices that utilize priority class detectors to identify highest priority matches in multiple CAM arrays and methods of operating same 有权
标题翻译：使用优先级检测器来识别多个CAM阵列中的最高优先级匹配的内容可寻址存储器（CAM）设备及其操作方法
公开(公告)号：US07092311B1
公开(公告)日：2006-08-15
申请号：US10386399
申请日：2003-03-11
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C15/04 , G11C5/14
CPC分类号： G11C15/00 , G11C15/04
摘要： Content addressable memory devices may include a priority encoder therein and a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of the priority encoder. A priority class detector is also provided for efficiently communicating match information that is generated during a search operation. The priority class detector passes match information from a selected priority class of rows in a selected one of the CAM arrays in the first tier to the priority encoder. This operation to pass match information is performed in response to detecting a match in the selected priority class when a search operation is performed. The priority class detector performs operations to locally encode match lines associated with a respective CAM array by priority class. These match lines are associated with a plurality of consecutive rows or consecutive pairs of rows that are arranged in a repeating priority class sequence comprising different priority classes. The priority class sequence may be an alternating priority class sequence, with each physically even row (or even pair of rows) in a CAM array being associated with one priority class and each physically odd row (or odd pair of rows) in a CAM array being associated within another priority class. Alternative priority class sequences may also be provided.
摘要翻译：在优先编码器的第一侧上，内容可寻址存储器设备可以包括其中的优先编码器和相对于彼此并排布置的第一层CAM阵列。还提供优先级检测器用于有效地传达在搜索操作期间产生的匹配信息。优先级检测器将匹配信息从第一层中所选择的一个CAM阵列中的所选择的优先级类别传递到优先级编码器。当执行搜索操作时，响应于检测到所选择的优先级类别中的匹配，执行用于传递匹配信息的该操作。优先级检测器执行操作以通过优先级来本地编码与相应CAM阵列相关联的匹配线。这些匹配线与以包括不同优先级等级的重复优先级序列排列的多个连续行或连续的行对相关联。优先级序列可以是交替优先级序列，CAM阵列中的每个物理偶数行（或甚至一对行）与CAM阵列中的一个优先级类别和每个物理上奇数行（或奇数行对）相关联）被关联在另一个优先级中。还可以提供替代的优先级序列。

4. 发明授权

US06240046B1 Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle 有权
标题翻译：能够在单个时钟周期内读取一个或多于一个数据字的集成电路随机存取存储器
公开(公告)号：US06240046B1
公开(公告)日：2001-05-29
申请号：US09502983
申请日：2000-02-11
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C800
CPC分类号： G11C7/065 , G11C7/12 , G11C7/22 , G11C8/08 , G11C11/4091 , G11C2207/229 , H01L27/10891 , H01L27/10897
摘要： A high performance random access memory integrated circuit is disclosed in several embodiments, along with various embodiments of associated supporting circuitry, which offers significant power savings in read operations. The integrated circuit is capable of retrieving data words from a memory array either one data word in a single clock cycle or more than one data word in a single clock cycle. For random memory reads, retrieving one data word from the memory array in a clock cycle where the memory array is accessed in response to each read request saves power over retrieving more than one data word from the memory array in the clock cycle. Conversely, if read requests are burst requests (i.e., a first read request immediately followed by advance requests), power is saved by retrieving more than one data word in a clock cycle where the memory array is accessed.
摘要翻译：多个实施例中公开了高性能随机存取存储器集成电路，以及相关支持电路的各种实施例，其在读取操作中提供了显着的功率节省。集成电路能够在单个时钟周期中从存储器阵列中检索数据字中的一个数据字，或者在单个时钟周期内从多个数据字中检索数据字。对于随机存储器读取，在响应于每个读取请求访问存储器阵列的时钟周期中从存储器阵列中检索一个数据字节省了在时钟周期中从存储器阵列中检索多于一个数据字的功率。相反，如果读请求是突发请求（即紧接着是高速请求的第一读请求），则通过在访问存储器阵列的时钟周期中检索多于一个数据字来节省功率。

5. 发明授权

US06208575B1 Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage 有权
标题翻译：动态存储器阵列位线读出放大器能够驱动到基本上达到电压源之前但是停止
公开(公告)号：US06208575B1
公开(公告)日：2001-03-27
申请号：US09503109
申请日：2000-02-11
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/08 , G11C2207/104 , G11C2207/229 , H01L27/10891 , H01L27/10897
摘要： A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. An exemplary 18 MBit memory array includes four banks of arrays. Within each memory bank, a row of bit line sense amplifiers is implemented in the holes between each pair of array blocks. After a selected word line is driven active, and a signal from each associated memory cell is developed on the corresponding bit line pair, both PMOS and NMOS sensing of the associated bit line sense amplifiers are simultaneously enabled. The PMOS sense amplifier drives the bit line having a higher voltage toward VDD, but this PMOS sensing is terminated before the high-going bit line substantially reaches the full VDD voltage, thus allowing the bit line to quickly be driven to a high level with a reduced “exponential tail.” NMOS sensing continues while the word line and array select lines are left high, so that charge sharing between the sense amplifier nodes, the bit lines, and the memory cell storage node itself contribute to determining the final restore level that is “written” back into the selected memory cell. The PMOS sense timing may be accomplished to ensure a written high level that is substantially independent of VDD and substantially independent of process and temperature variations. The selected word line is then brought low, the NMOS sensing terminated, and the array block precharged.
摘要翻译：多个实施例中公开了高性能动态存储器阵列结构以及相关支持电路的各种实施例。一个示例性的18 MBit存储器阵列包括四组阵列。在每个存储体内，在每对阵列块之间的孔中实施一排位线读出放大器。在选择的字线被驱动为有效并且来自每个相关联的存储器单元的信号在对应的位线对上被开发之后，相关联的位线读出放大器的PMOS和NMOS感测同时被使能。 PMOS读出放大器驱动具有较高电压的位线朝向VDD，但是该PMOS感测在高位位线基本上达到全VDD电压之前终止，从而允许位线快速驱动到高电平减少“指数尾”。当字线和阵列选择线保持为高电平时，NMOS感测继续进行，使得感测放大器节点，位线和存储器单元存储节点本身之间的电荷共享有助于确定“写入”的最终恢复电平所选存储单元。可以实现PMOS检测定时，以确保基本上与VDD无关的写入高电平，并且基本上与过程和温度变化无关。所选择的字线然后被置为低电平，NMOS感测终止，并且阵列块被预充电。

6. 发明授权

US06198682B1 Hierarchical dynamic memory array architecture using read amplifiers separate from bit line sense amplifiers 有权
标题翻译：使用与位线读出放大器分离的读取放大器的分层动态存储器阵列架构
公开(公告)号：US06198682B1
公开(公告)日：2001-03-06
申请号：US09329975
申请日：1999-06-10
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C700
CPC分类号： H01L27/10897 , G11C7/04 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/08 , G11C2207/104 , G11C2207/229 , H01L27/10891
摘要： A high performance dynamic memory array architecture includes a row of bit line sense amplifiers between array blocks. Each bit line sense amplifier is shared between two pairs of bit lines. Half of the bit line pairs within each array block are served by a sense amplifier located above the array block, and the remaining half are served by a sense amplifier located below the array block. A read amplifier in the read path, which is separate from the bit line sense amplifier, is used to develop signal on a bus line before bit line sensing has occurred. This read amplifier may be connected to the bit lines, the internal sense amplifier nodes, a local I/O line, or a local output line. In a preferred embodiment, a second stage amplifier further buffers the signal and drives a pair of global output lines which extend the full height of the memory bank to respective I/O circuits.
摘要翻译：高性能动态存储器阵列架构包括阵列块之间的一行位线读出放大器。每个位线读出放大器在两对位线之间共享。每个阵列块内的位线对中的一半由位于阵列块上方的读出放大器提供，剩余的一半由位于阵列块下方的读出放大器提供。在位线检测发生之前，读取路径中与位线读出放大器分离的读取放大器用于在总线上产生信号。该读取放大器可以连接到位线，内部读出放大器节点，本地I / O线或本地输出线。在优选实施例中，第二级放大器进一步缓冲信号并驱动一对全局输出线，其将存储体的整个高度延伸到相应的I / O电路。

7. 发明授权

US6044023A Method and apparatus for pipelining data in an integrated circuit 失效
标题翻译：用于在集成电路中流水线数据的方法和装置
公开(公告)号：US6044023A
公开(公告)日：2000-03-28
申请号：US53423
申请日：1998-04-01
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G06F9/38 , G11C7/06 , G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/06 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.
摘要翻译：用于流水线数据的方法和装置用于同步集成存储器电路，其中读周期由在时钟输入端接收的第一时钟启动。与读周期相关的数据通过存储器异步传播，产生数据，然后输入到流水线电路。该装置包括具有精确定时的转向电路，用于将在读周期中产生的数据转换成寄存器的多个分支中断定的一个。选择电路用于选择在接收到后续时钟时输出已经存储在断言的分支中的数据。随后的时钟是在第一个时钟之后发生可编程数量的时钟的时钟。

8. 发明授权

US5995437A Semiconductor memory and method of accessing memory arrays 失效
标题翻译：半导体存储器和访问存储器阵列的方法
公开(公告)号：US5995437A
公开(公告)日：1999-11-30
申请号：US83334
申请日：1998-05-21
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C8/12 , G11C8/00
CPC分类号： G11C8/12
摘要： Accessing of adjacent arrays of memory in a semiconductor integrated circuit is facilitated by numbering the arrays of memory in accordance with a digital Gray code in which the addresses of adjacent arrays differ in only one digit. Each array is selected by the full array select address field. Each sense amplifier and I/O circuitry between memory arrays and shared by two adjacent memory arrays is selected by the full array select address field less one bit, that bit being the single address bit that differs between the addresses of the two adjacent Grey code numbered memory arrays. This permits faster decoding and enabling of the sense amplifier and I/O signal circuitry.
摘要翻译：通过根据其中相邻阵列的地址仅在一个数字不同的数字格雷码对存储器阵列进行编号，便于访问半导体集成电路中相邻的存储器阵列。每个阵列由完整阵列选择地址字段选择。存储器阵列之间的每个读出放大器和I / O电路由两个相邻的存储器阵列共享，由全部阵列选择地址字段选择较少一位，该位是在两个相邻的格雷码的地址之间不同的单个地址位存储器阵列。这允许读出放大器和I / O信号电路更快的解码和使能。

9. 发明授权

US5737267A Word line driver circuit 失效
标题翻译：字线驱动电路
公开(公告)号：US5737267A
公开(公告)日：1998-04-07
申请号：US630310
申请日：1996-04-10
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C11/407 , G11C8/08 , G11C11/408 , G11C13/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： An improved method and circuit for a word line driver in memory integrated circuits is disclosed. Instead of connecting the gate terminal of an isolation transistor to a constant high power supply voltage, the present invention momentarily boosts the voltage at the gate terminal to allow for a full logic high voltage to be transferred to the gate terminal of a word line driver transistor. Then the voltage at the gate terminal of the isolation transistor is reduced to its original level before the signal at the drain terminal of the word line driver transistor is boosted from ground to voltages above the power supply level. Thus, a maximized boosted voltage is trapped at the gate terminal of the word line driver transistor to improve the drive capability of the word line driver transistor.
摘要翻译：公开了用于存储器集成电路中的字线驱动器的改进方法和电路。代替将隔离晶体管的栅极端子连接到恒定的高电源电压，本发明立即升高栅极端子处的电压，以使全逻辑高电压被传送到字线驱动晶体管的栅极端子。然后，在字线驱动晶体管的漏极端子处的信号从地电压升至高于电源电平的电压之前，隔离晶体管的栅极端子处的电压降低到其原始电平。因此，最大化的升压电压被捕获在字线驱动晶体管的栅极端，以提高字线驱动晶体管的驱动能力。

10. 发明授权

US4716380A FET differential amplifier 失效
标题翻译： FET差分放大器
公开(公告)号：US4716380A
公开(公告)日：1987-12-29
申请号：US633375
申请日：1984-07-23
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： H03F3/45
CPC分类号： H03F3/45076
摘要： A differential amplifier (10) has two input terminals (16,18), an output terminal (20) together with power terminals (12,14). The differential amplifier comprises two or more stages with each stage having a pull-up transistor (22) and a pull-down transistor (26). The first input terminal (16) is connected to alternate stages of the amplifier (10) and the second input terminal (18) is connected to the remaining alternate stages of the amplifier (10). The gain of the various stages is determined by fabrication of the transistors, in particular, the geometries of the transistor channels. A state transition at an output terminal (20) is produced when the voltages at the input terminals (16,18) are approximately equal and the gains of the various stages are essentially equal. A state change at the output terminal (20) is caused to occur when there is a given voltage offset between the voltages at the input terminal (16,18) when the gains of the two sets of alternate stages of the amplifier (10) are made unequal.
摘要翻译：差分放大器（10）具有两个输入端子（16,18），输出端子（20）和电源端子（12,14）。差分放大器包括两级或更多级，其中每级具有上拉晶体管（22）和下拉晶体管（26）。第一输入端子（16）连接到放大器（10）的交替级，并且第二输入端子（18）连接到放大器（10）的其余交替级。通过晶体管的制造，特别是晶体管通道的几何形状来确定各个阶段的增益。当输入端子（16,18）处的电压近似相等并且各级的增益基本上相等时，产生输出端子（20）处的状态转变。当放大器（10）的两组交替级的增益分别是在输入端（16,18）处的电压之间存在给定的电压偏移时，在输出端子（20）处的状态变化被发生不平等

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