专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5680360A Circuits for improving the reliablity of antifuses in integrated circuits 失效
标题翻译：用于提高集成电路中反熔丝可靠性的电路
公开(公告)号：US5680360A
公开(公告)日：1997-10-21
申请号：US473039
申请日：1995-06-06
申请人： David J. Pilling , Raymond M. Chu , Sik K. Lui
发明人： David J. Pilling , Raymond M. Chu , Sik K. Lui
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18
摘要： A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish this, an antifuse has applied across its two terminals a "reading" or "evaluation" voltage as required by the system operation for a single read or evaluation clock period (typically 5 ns to 30 ns in duration). The signal describing the state of the antifuse is then stored in a latch, register, or other suitable structure for subsequent sampling. In this manner, a low read current flows in the antifuse in response to the standard chip operating voltage for only a short period of time such as a single clock cycle. Thus, continuous voltages across the two terminals of the antifuse are avoided and an unprogrammed antifuse is not inadvertently programmed and a programmed antifuse is not inadvertently converted back to its high impedance state (i.e. "unprogrammed"). In another embodiment, a multiplexer coupled to a terminal of the antifuse switches the terminal of the antifuse to a programming voltage node when the antifuse is selected for programming and to a reference voltage source when the antifuse is not selected for programming. The multiplexer prevents undesired voltages from being applied across the antifuse while other antifuses are being programmed. The two embodiments discussed may be used in conjunction with each other or separately.
摘要翻译：电路通过基本消除反熔丝端子上的电压的连续不期望的应用来提高某些类型系统中反熔丝的可靠性。为了实现这一点，反熔丝在其两个端子上施加了对于单个读取或评估时钟周期（通常为5ns至30ns的持续时间）的系统操作所需的“读取”或“评估”电压。然后将描述反熔丝的状态的信号存储在锁存器，寄存器或其他合适的结构中，用于随后的采样。以这种方式，仅在短时间段（例如单个时钟周期）内，低反向电流响应于标准芯片工作电压而流过反熔丝。因此，避免了反熔丝两端的连续电压，并且不会无意地编程未编程的反熔丝，并且编程的反熔丝不会无意中转换回其高阻抗状态（即“未编程”）。在另一个实施例中，当反熔丝被选择用于编程时，耦合到反熔丝的端子的多路复用器将反熔丝的端子切换到编程电压节点，并且当反熔丝未被选择用于编程时，将其转换为参考电压源。多路复用器防止在反熔丝跨越反熔丝而施加不需要的电压，而其他反熔丝被编程。所讨论的两个实施例可以彼此结合使用或分开使用。

2. 发明授权

US5838624A Circuits for improving the reliability of antifuses in integrated circuits 失效
标题翻译：用于提高集成电路中反熔丝可靠性的电路
公开(公告)号：US5838624A
公开(公告)日：1998-11-17
申请号：US850902
申请日：1997-05-02
申请人： David J. Pilling , Raymond M. Chu , Sik K. Lui
发明人： David J. Pilling , Raymond M. Chu , Sik K. Lui
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18
摘要： A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish this, an antifuse has applied across its two terminals a "reading" or "evaluation" voltage as required by the system operation for a single read or evaluation clock period (typically 5 ns to 30 ns in duration). The signal describing the state of the antifuse is then stored in a latch, register, or other suitable structure for subsequent sampling. In this manner, a low read current flows in the antifuse in response to the standard chip operating voltage for only a short period of time such as a single clock cycle. Thus, continuous voltages across the two terminals of the antifuse are avoided and an unprogrammed antifuse is not inadvertently programmed and a programmed antifuse is not inadvertently converted back to its high impedance state (i.e. "unprogrammed"). In another embodiment, a multiplexer coupled to a terminal of the antifuse switches the terminal of the antifuse to a programming voltage node when the antifuse is selected for programming and to a reference voltage source when the antifuse is not selected for programming. The multiplexer prevents undesired voltages from being applied across the antifuse while other antifuses are being programmed. The two embodiments discussed may be used in conjunction with each other or separately.
摘要翻译：电路通过基本消除反熔丝端子上的电压的连续不期望的应用来提高某些类型系统中反熔丝的可靠性。为了实现这一点，反熔丝在其两个端子上施加了对于单个读取或评估时钟周期（通常为5ns至30ns的持续时间）的系统操作所需的“读取”或“评估”电压。然后将描述反熔丝的状态的信号存储在锁存器，寄存器或其他合适的结构中，用于随后的采样。以这种方式，仅在短时间段（例如单个时钟周期）内，低反向电流响应于标准芯片工作电压而流过反熔丝。因此，避免了反熔丝两端的连续电压，并且不会无意地编程未编程的反熔丝，并且编程的反熔丝不会无意中转换回其高阻抗状态（即“未编程”）。在另一个实施例中，当反熔丝被选择用于编程时，耦合到反熔丝的端子的多路复用器将反熔丝的端子切换到编程电压节点，并且当反熔丝未被选择用于编程时，将其转换为参考电压源。多路复用器防止在反熔丝跨越反熔丝而施加不需要的电压，而其他反熔丝被编程。所讨论的两个实施例可以彼此结合使用或分开使用。

3. 发明授权

US5677888A Redundancy circuit for programmable integrated circuits 失效
标题翻译：可编程集成电路冗余电路
公开(公告)号：US5677888A
公开(公告)日：1997-10-14
申请号：US473041
申请日：1995-06-06
申请人： Sik K. Lui , Raymond M. Chu , David J. Pilling
发明人： Sik K. Lui , Raymond M. Chu , David J. Pilling
IPC分类号： G06F11/00 , G11C17/16 , G11C17/18 , G11C29/00
CPC分类号： G11C29/781 , G06F11/00 , G11C17/16 , G11C17/18 , G11C29/785 , Y10S257/919
摘要： An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.
摘要翻译：反熔丝冗余电路对外部电路和用户具有透明度。在一个实施例中，反熔丝冗余电路包括两个反熔丝而不是一个。电路被布置成使得两个反熔丝可以被同时编程和读取。如果在不编写其他反熔丝的情况下对单个反熔丝进行编程，则反熔丝冗余电路将注册编程的反熔丝。此外，如果在冗余电路中的两个反熔丝编程之后，单个编程的反熔丝被无意地解除编程，则反熔丝冗余电路将继续注册编程的反熔丝。结果是制造产量的增加和利用反熔丝的集成电路的可靠性的增加。

4. 发明授权

US5818778A Redundancy circuit for programmable integrated circuits 失效
标题翻译：可编程集成电路冗余电路
公开(公告)号：US5818778A
公开(公告)日：1998-10-06
申请号：US824591
申请日：1997-03-26
申请人： Sik K. Lui , Raymond M. Chu , David J. Pilling
发明人： Sik K. Lui , Raymond M. Chu , David J. Pilling
IPC分类号： G06F11/00 , G11C17/16 , G11C17/18 , G11C29/00
CPC分类号： G11C29/781 , G06F11/00 , G11C17/16 , G11C17/18 , G11C29/785 , Y10S257/919
摘要： An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.
摘要翻译：反熔丝冗余电路对外部电路和用户具有透明度。在一个实施例中，反熔丝冗余电路包括两个反熔丝而不是一个。电路被布置成使得两个反熔丝可以被同时编程和读取。如果在不编写其他反熔丝的情况下对单个反熔丝进行编程，则反熔丝冗余电路将注册编程的反熔丝。此外，如果在冗余电路中的两个反熔丝编程之后，单个编程的反熔丝被无意地解除编程，则反熔丝冗余电路将继续注册编程的反熔丝。结果是制造产量的增加和利用反熔丝的集成电路的可靠性的增加。

5. 发明授权

US5514980A High resolution circuit and method for sensing antifuses 失效
标题翻译：高分辨率电路和感应反熔丝的方法
公开(公告)号：US5514980A
公开(公告)日：1996-05-07
申请号：US456991
申请日：1995-05-31
申请人： David J. Pilling , Raymond M. Chu , Sik K. Lui
发明人： David J. Pilling , Raymond M. Chu , Sik K. Lui
IPC分类号： G11C7/06 , G11C17/18 , G11C29/00 , H01H37/76
CPC分类号： G11C29/785 , G11C17/18 , G11C7/065 , G11C29/781
摘要： A high resolution sense amplifier and method for sensing the state of antifuses in an integrated circuit is capable of correctly reading even a defectively programmed antifuse having a resistance of up to 20 K.OMEGA. as being programmed. The sense amplifier reads two antifuses at each programmable location, and correctly reads that location as being programmed if either or both of the antifuses at that location have been blown.
摘要翻译：用于感测集成电路中的反熔丝状态的高分辨率感测放大器和方法能够正确地读取甚至编程的具有高达20K欧姆电阻的缺陷编程的反熔丝。读出放大器在每个可编程位置读取两个反熔丝，并且如果该位置的任何一个或两个反熔丝已经被熔断，则正确读取该位置。

6. 发明申请

US20160247899A1 POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS 审中-公开
标题翻译：功率MOSFET器件结构高频应用
公开(公告)号：US20160247899A1
公开(公告)日：2016-08-25
申请号：US14629229
申请日：2015-02-23
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L29/423 , H01L21/3213 , H01L29/08
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

7. 发明授权

US08597998B2 Power MOS device fabrication 有权
标题翻译：功率MOS器件制造
公开(公告)号：US08597998B2
公开(公告)日：2013-12-03
申请号：US13604286
申请日：2012-09-05
申请人： Anup Bhalla , Sik K. Lui , Tiesheng Li
发明人： Anup Bhalla , Sik K. Lui , Tiesheng Li
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成掩模; 通过掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 取下面罩离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 在源体接触沟槽中形成插塞，其中插头延伸到身体区域的底部下方; 并且在所述源体接触沟槽中，在所述插头的顶部上设置导电材料。

8. 发明授权

US08288229B2 Power MOS device fabrication 有权
标题翻译：功率MOS器件制造
公开(公告)号：US08288229B2
公开(公告)日：2012-10-16
申请号：US13043721
申请日：2011-03-09
申请人： Anup Bhalla , Sik K. Lui , Tiesheng Li
发明人： Anup Bhalla , Sik K. Lui , Tiesheng Li
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a hard mask on the substrate having a top substrate surface; forming a gate trench in the substrate, through the hard mask; depositing gate material in the gate trench; removing the hard mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; and disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成硬掩模; 通过硬掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 去除硬掩模离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 以及沿着所述沟槽壁的至少一部分而不是沿着所述沟槽底部布置抗穿孔植入物。

9. 发明授权

US08169062B2 Integrated circuit package for semiconductior devices with improved electric resistance and inductance 有权
标题翻译：具有改善电阻和电感的半导体器件的集成电路封装
公开(公告)号：US08169062B2
公开(公告)日：2012-05-01
申请号：US13114063
申请日：2011-05-24
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/495 , H01L23/48 , H01L29/40 , H01L23/52
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

10. 发明授权

US08163618B2 Power MOSFET device structure for high frequency applications 有权
标题翻译：功率MOSFET器件结构用于高频应用
公开(公告)号：US08163618B2
公开(公告)日：2012-04-24
申请号：US12658450
申请日：2010-02-09
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式