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1. 发明授权

US5680360A Circuits for improving the reliablity of antifuses in integrated circuits 失效
标题翻译：用于提高集成电路中反熔丝可靠性的电路
公开(公告)号：US5680360A
公开(公告)日：1997-10-21
申请号：US473039
申请日：1995-06-06
申请人： David J. Pilling , Raymond M. Chu , Sik K. Lui
发明人： David J. Pilling , Raymond M. Chu , Sik K. Lui
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18
摘要： A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish this, an antifuse has applied across its two terminals a "reading" or "evaluation" voltage as required by the system operation for a single read or evaluation clock period (typically 5 ns to 30 ns in duration). The signal describing the state of the antifuse is then stored in a latch, register, or other suitable structure for subsequent sampling. In this manner, a low read current flows in the antifuse in response to the standard chip operating voltage for only a short period of time such as a single clock cycle. Thus, continuous voltages across the two terminals of the antifuse are avoided and an unprogrammed antifuse is not inadvertently programmed and a programmed antifuse is not inadvertently converted back to its high impedance state (i.e. "unprogrammed"). In another embodiment, a multiplexer coupled to a terminal of the antifuse switches the terminal of the antifuse to a programming voltage node when the antifuse is selected for programming and to a reference voltage source when the antifuse is not selected for programming. The multiplexer prevents undesired voltages from being applied across the antifuse while other antifuses are being programmed. The two embodiments discussed may be used in conjunction with each other or separately.
摘要翻译：电路通过基本消除反熔丝端子上的电压的连续不期望的应用来提高某些类型系统中反熔丝的可靠性。为了实现这一点，反熔丝在其两个端子上施加了对于单个读取或评估时钟周期（通常为5ns至30ns的持续时间）的系统操作所需的“读取”或“评估”电压。然后将描述反熔丝的状态的信号存储在锁存器，寄存器或其他合适的结构中，用于随后的采样。以这种方式，仅在短时间段（例如单个时钟周期）内，低反向电流响应于标准芯片工作电压而流过反熔丝。因此，避免了反熔丝两端的连续电压，并且不会无意地编程未编程的反熔丝，并且编程的反熔丝不会无意中转换回其高阻抗状态（即“未编程”）。在另一个实施例中，当反熔丝被选择用于编程时，耦合到反熔丝的端子的多路复用器将反熔丝的端子切换到编程电压节点，并且当反熔丝未被选择用于编程时，将其转换为参考电压源。多路复用器防止在反熔丝跨越反熔丝而施加不需要的电压，而其他反熔丝被编程。所讨论的两个实施例可以彼此结合使用或分开使用。

2. 发明授权

US5838624A Circuits for improving the reliability of antifuses in integrated circuits 失效
标题翻译：用于提高集成电路中反熔丝可靠性的电路
公开(公告)号：US5838624A
公开(公告)日：1998-11-17
申请号：US850902
申请日：1997-05-02
申请人： David J. Pilling , Raymond M. Chu , Sik K. Lui
发明人： David J. Pilling , Raymond M. Chu , Sik K. Lui
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18
摘要： A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish this, an antifuse has applied across its two terminals a "reading" or "evaluation" voltage as required by the system operation for a single read or evaluation clock period (typically 5 ns to 30 ns in duration). The signal describing the state of the antifuse is then stored in a latch, register, or other suitable structure for subsequent sampling. In this manner, a low read current flows in the antifuse in response to the standard chip operating voltage for only a short period of time such as a single clock cycle. Thus, continuous voltages across the two terminals of the antifuse are avoided and an unprogrammed antifuse is not inadvertently programmed and a programmed antifuse is not inadvertently converted back to its high impedance state (i.e. "unprogrammed"). In another embodiment, a multiplexer coupled to a terminal of the antifuse switches the terminal of the antifuse to a programming voltage node when the antifuse is selected for programming and to a reference voltage source when the antifuse is not selected for programming. The multiplexer prevents undesired voltages from being applied across the antifuse while other antifuses are being programmed. The two embodiments discussed may be used in conjunction with each other or separately.
摘要翻译：电路通过基本消除反熔丝端子上的电压的连续不期望的应用来提高某些类型系统中反熔丝的可靠性。为了实现这一点，反熔丝在其两个端子上施加了对于单个读取或评估时钟周期（通常为5ns至30ns的持续时间）的系统操作所需的“读取”或“评估”电压。然后将描述反熔丝的状态的信号存储在锁存器，寄存器或其他合适的结构中，用于随后的采样。以这种方式，仅在短时间段（例如单个时钟周期）内，低反向电流响应于标准芯片工作电压而流过反熔丝。因此，避免了反熔丝两端的连续电压，并且不会无意地编程未编程的反熔丝，并且编程的反熔丝不会无意中转换回其高阻抗状态（即“未编程”）。在另一个实施例中，当反熔丝被选择用于编程时，耦合到反熔丝的端子的多路复用器将反熔丝的端子切换到编程电压节点，并且当反熔丝未被选择用于编程时，将其转换为参考电压源。多路复用器防止在反熔丝跨越反熔丝而施加不需要的电压，而其他反熔丝被编程。所讨论的两个实施例可以彼此结合使用或分开使用。

3. 发明授权

US5677888A Redundancy circuit for programmable integrated circuits 失效
标题翻译：可编程集成电路冗余电路
公开(公告)号：US5677888A
公开(公告)日：1997-10-14
申请号：US473041
申请日：1995-06-06
申请人： Sik K. Lui , Raymond M. Chu , David J. Pilling
发明人： Sik K. Lui , Raymond M. Chu , David J. Pilling
IPC分类号： G06F11/00 , G11C17/16 , G11C17/18 , G11C29/00
CPC分类号： G11C29/781 , G06F11/00 , G11C17/16 , G11C17/18 , G11C29/785 , Y10S257/919
摘要： An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.
摘要翻译：反熔丝冗余电路对外部电路和用户具有透明度。在一个实施例中，反熔丝冗余电路包括两个反熔丝而不是一个。电路被布置成使得两个反熔丝可以被同时编程和读取。如果在不编写其他反熔丝的情况下对单个反熔丝进行编程，则反熔丝冗余电路将注册编程的反熔丝。此外，如果在冗余电路中的两个反熔丝编程之后，单个编程的反熔丝被无意地解除编程，则反熔丝冗余电路将继续注册编程的反熔丝。结果是制造产量的增加和利用反熔丝的集成电路的可靠性的增加。

4. 发明授权

US5514980A High resolution circuit and method for sensing antifuses 失效
标题翻译：高分辨率电路和感应反熔丝的方法
公开(公告)号：US5514980A
公开(公告)日：1996-05-07
申请号：US456991
申请日：1995-05-31
申请人： David J. Pilling , Raymond M. Chu , Sik K. Lui
发明人： David J. Pilling , Raymond M. Chu , Sik K. Lui
IPC分类号： G11C7/06 , G11C17/18 , G11C29/00 , H01H37/76
CPC分类号： G11C29/785 , G11C17/18 , G11C7/065 , G11C29/781
摘要： A high resolution sense amplifier and method for sensing the state of antifuses in an integrated circuit is capable of correctly reading even a defectively programmed antifuse having a resistance of up to 20 K.OMEGA. as being programmed. The sense amplifier reads two antifuses at each programmable location, and correctly reads that location as being programmed if either or both of the antifuses at that location have been blown.
摘要翻译：用于感测集成电路中的反熔丝状态的高分辨率感测放大器和方法能够正确地读取甚至编程的具有高达20K欧姆电阻的缺陷编程的反熔丝。读出放大器在每个可编程位置读取两个反熔丝，并且如果该位置的任何一个或两个反熔丝已经被熔断，则正确读取该位置。

5. 发明授权

US5818778A Redundancy circuit for programmable integrated circuits 失效
标题翻译：可编程集成电路冗余电路
公开(公告)号：US5818778A
公开(公告)日：1998-10-06
申请号：US824591
申请日：1997-03-26
申请人： Sik K. Lui , Raymond M. Chu , David J. Pilling
发明人： Sik K. Lui , Raymond M. Chu , David J. Pilling
IPC分类号： G06F11/00 , G11C17/16 , G11C17/18 , G11C29/00
CPC分类号： G11C29/781 , G06F11/00 , G11C17/16 , G11C17/18 , G11C29/785 , Y10S257/919
摘要： An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.
摘要翻译：反熔丝冗余电路对外部电路和用户具有透明度。在一个实施例中，反熔丝冗余电路包括两个反熔丝而不是一个。电路被布置成使得两个反熔丝可以被同时编程和读取。如果在不编写其他反熔丝的情况下对单个反熔丝进行编程，则反熔丝冗余电路将注册编程的反熔丝。此外，如果在冗余电路中的两个反熔丝编程之后，单个编程的反熔丝被无意地解除编程，则反熔丝冗余电路将继续注册编程的反熔丝。结果是制造产量的增加和利用反熔丝的集成电路的可靠性的增加。

6. 发明授权

US5950233A Interleaved burst address counter with reduced delay between rising clock edge and burst address transfer to memory 失效
标题翻译：交错突发地址计数器，在上升时钟沿和突发地址传输到存储器之间的延迟减小
公开(公告)号：US5950233A
公开(公告)日：1999-09-07
申请号：US755074
申请日：1996-11-21
申请人： Raymond M. Chu , David J. Pilling , John R. Mick
发明人： Raymond M. Chu , David J. Pilling , John R. Mick
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/161
摘要： A burst address sequencer and method for providing sequential addresses to a memory which operates in response to a clock signal. The burst address sequencer includes a plurality of two-stage address registers, with an address register being provided for each address bit. Prior to an initial rising edge of the clock signal, an initial address is loaded into the first stages of the two-stage address registers. In response to the initial rising edge of the clock signal, the initial address is clocked through the second stages of the two-stage address registers, directly to the memory. Subsequent addresses are derived from the initial address by circuitry within the burst address sequencer. These subsequent burst addresses are provided to the first stages of the addresses registers prior to subsequent rising edges of the clock signal and clocked out to the memory in response to these subsequent rising edges of the clock signal. By providing the addresses directly from the second stage of the address registers to the memory, the logic gate delay associated with providing the addresses to the memory in response to the rising edge of the clock signal is minimized.
摘要翻译：一种突发地址定序器和方法，用于向响应于时钟信号操作的存储器提供顺序地址。突发地址定序器包括多个两级地址寄存器，其中为每个地址位提供地址寄存器。在时钟信号的初始上升沿之前，初始地址被加载到两级地址寄存器的第一级。响应于时钟信号的初始上升沿，初始地址通过两级地址寄存器的第二级被直接送到存储器。随后的地址由突发地址定序器内的电路从初始地址中导出。这些后续突发地址在时钟信号的后续上升沿之前被提供给地址寄存器的第一级，并且响应于时钟信号的这些随后的上升沿而被输出到存储器。通过从地址寄存器的第二级直接提供地址到存储器，使得响应于时钟信号的上升沿向存储器提供地址的逻辑门延迟最小化。

7. 发明授权

US5808343A Input structure for digital integrated circuits 失效
标题翻译：数字集成电路的输入结构
公开(公告)号：US5808343A
公开(公告)日：1998-09-15
申请号：US716961
申请日：1996-09-20
申请人： David J. Pilling , Raymond M. Chu
发明人： David J. Pilling , Raymond M. Chu
IPC分类号： H01L27/08 , H01L23/62 , H01L29/00
CPC分类号： H01L27/0802
摘要： Integrated circuit access times are reduced by an input structure in which input signals are routed through a low resistance path from the input pad directly to the interior of the integrated circuit without using an input driver.
摘要翻译：通过输入结构减少集成电路访问时间，其中输入信号通过低电阻路径从输入焊盘直接引导到集成电路的内部，而不使用输入驱动器。

8. 发明授权

US08041552B2 Behavioral modeling of high speed differential signals based on physical characteristics 有权
标题翻译：基于物理特性的高速差分信号的行为建模
公开(公告)号：US08041552B2
公开(公告)日：2011-10-18
申请号：US11786175
申请日：2007-04-10
申请人： David J. Pilling
发明人： David J. Pilling
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizing that parameter is constructed. The behavioral model can then be utilized to predict the behavior of the integrated circuit output drivers.
摘要翻译：提供了一种对集成电路中的输出驱动器进行建模的方法，例如串行器/解串器电路。根据本发明的实施例，物理地测量电路的至少一个参数，并构建利用该参数的行为模型。然后可以利用行为模型来预测集成电路输出驱动器的行为。

9. 发明授权

US5608685A Adjacent row shift redundancy circuit having signal restorer coupled to programmable links and a method thereof 失效
标题翻译：具有耦合到可编程链路的信号恢复器的相邻行移位冗余电路及其方法
公开(公告)号：US5608685A
公开(公告)日：1997-03-04
申请号：US451708
申请日：1995-05-26
申请人： Larry D. Johnson , David J. Pilling
发明人： Larry D. Johnson , David J. Pilling
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/787
摘要： A redundancy circuit for a semiconductor memory device utilizes a fuse ladder comprising alternating programmable resistive fuses and signal restorers connected to one another in series. The signal restorers coupled between the fuses prevent the formation of a high impedance resistive line with a floating node when one of the fuses in the ladder is blown.
摘要翻译：用于半导体存储器件的冗余电路利用包括交替可编程电阻熔丝和信号恢复器的熔丝梯，所述可编程电阻熔丝和信号恢复器彼此串联连接。耦合在保险丝之间的信号恢复器防止当梯子中的一个保险丝熔断时形成具有浮动节点的高阻抗电阻线。

10. 发明授权

US5325335A Memories and amplifiers suitable for low voltage power supplies 失效
标题翻译：适用于低压电源的存储器和放大器
公开(公告)号：US5325335A
公开(公告)日：1994-06-28
申请号：US894414
申请日：1992-06-05
申请人： Michael A. Ang , David J. Pilling
发明人： Michael A. Ang , David J. Pilling
IPC分类号： G11C7/06 , G11C11/419 , G11C11/40
CPC分类号： G11C7/065 , G11C11/419
摘要： A sense amplifier for a static memory includes two pull-up transistors. The gate of each transistor is coupled to the drain of the other transistor. A circuitry is provided for precharging the drains of both pull-up transistors to a selected voltage such that by the start of the tracking stage of the amplifier, both pull-up transistors are off. If the tracking stage is long enough, one pull-up transistor turns on while the other one remains off, so that before the start of the sensing stage both pull-up transistors reach their final ON/OFF states. Hence the amplifier is fast and power efficient. The memory bit lines are precharged to VCC before the tracking stage, improving the read-disturb immunity and hence allowing a wider range of voltages on the bit lines and the sense amplifier inputs. The noise immunity and tolerance to temperature process variations are improved as a result. The high noise immunity make the amplifier and the memory suitable for integration with noisy circuits such as CPUs. High speed, high power efficiency, high noise immunity, high tolerance to temperature and process variations and high permissible range of bit line voltages make the memory and the amplifier suitable for low-voltage power supplies such as VCC=3.0 V supplies used in lap-top, notebook, sub-note book, and hand-held computers.
摘要翻译：用于静态存储器的读出放大器包括两个上拉晶体管。每个晶体管的栅极耦合到另一个晶体管的漏极。提供了一种用于将两个上拉晶体管的漏极预充电到所选电压的电路，使得通过放大器的跟踪级开始，两个上拉晶体管截止。如果跟踪阶段足够长，则一个上拉晶体管导通，而另一个上拉晶体管导通，因此在感测阶段开始之前，两个上拉晶体管都达到其最终的ON / OFF状态。因此，放大器是快速和功率效率。在跟踪阶段之前，存储器位线被预充电到VCC，从而提高读干扰抗扰度，从而允许位线和读出放大器输入端的电压范围更宽。结果，噪声抗扰度和对温度变化的耐受性得到改善。高抗噪性使放大器和存储器适合与诸如CPU之类的噪声电路集成。高速，高功率效率，高抗噪声能力，高耐温度和工艺变化以及高位允许范围的位线电压使存储器和放大器适用于低压电源，如VCC = 3.0 V电源，顶部，笔记本，子笔记本和手持电脑。

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