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1. 发明授权

US06496911B1 Apparatus for memory bus tuning and methods therefor 有权
标题翻译：用于存储器总线调谐的装置及其方法
公开(公告)号：US06496911B1
公开(公告)日：2002-12-17
申请号：US09165954
申请日：1998-10-02
申请人： Robert Christopher Dixon , Thoi Nguyen , Tuan Hoang Nguyen
发明人： Robert Christopher Dixon , Thoi Nguyen , Tuan Hoang Nguyen
IPC分类号： G06F1200
CPC分类号： G06F13/4239 , G06F13/4072
摘要： An apparatus and method for memory bus tuning are implemented. A plurality of drivers having a plurality of selectable drive levels are coupled to a memory bus. The memory bus is connected to a memory device which may have a variable amount of memory, which may be in the form of dual-in-line memory modules (DIMM). A drive level is selected in response to a determination of the amount of memory included in the memory device. A register operable for receiving a data value corresponding to the amount of memory is coupled to the drivers, the drive level being selected thereby.
摘要翻译：实现用于存储器总线调谐的装置和方法。具有多个可选驱动电平的多个驱动器耦合到存储器总线。存储器总线连接到可能具有可变量的存储器的存储器件，存储器可以是双列直插存储器模块（DIMM）的形式。响应于确定包括在存储器件中的存储器的量来选择驱动器电平。可操作用于接收与存储器量相对应的数据值的寄存器耦合到驱动器，从而选择驱动级。

2. 发明授权

US06657325B2 Multiple fan sensing circuit and method for monitoring multiple cooling fans utilizing a single fan sense input 有权
标题翻译：多风扇感测电路和方法，用于利用单个风扇感测输入来监测多个冷却风扇
公开(公告)号：US06657325B2
公开(公告)日：2003-12-02
申请号：US09758863
申请日：2001-01-11
申请人： Robert Christopher Dixon , Thoi Nguyen
发明人： Robert Christopher Dixon , Thoi Nguyen
IPC分类号： H02J700
CPC分类号： H05K7/20836 , G06F1/20 , H05K7/20209
摘要： A multiple fan sensing circuit for use with a single fan sense input and method of operation thereof. The multiple fan sensing circuit includes a logic circuit, coupled to the fan sense input, that combines feedback signals from a first fan and a second fan. The first fan generates a tach signal indicative of the first fan operation and the second fan, e.g., a stuck rotor type fan, generates either an ON or OFF signal indicative of the second fan operation. In a related embodiment, the second fan generates a logic high signal in response to a failure in the second fan. In an advantageous embodiment, the logic circuit is a connector and a logic low level in the combined operational signal indicates a failed fan.
摘要翻译：一种用于单风扇感测输入的多风扇感测电路及其操作方法。多风扇感测电路包括耦合到风扇感测输入的逻辑电路，其组合来自第一风扇和第二风扇的反馈信号。第一风扇产生指示第一风扇操作的tach信号，并且第二风扇（例如，卡住的转子型风扇）产生指示第二风扇操作的ON或OFF信号。在相关实施例中，第二风扇响应于第二风扇的故障而产生逻辑高电平信号。在有利的实施例中，逻辑电路是连接器，并且组合的操作信号中的逻辑低电平指示故障风扇。

3. 发明授权

US06081862A Switching system for optimization of signal reflection 失效
标题翻译：用于信号反射优化的开关系统
公开(公告)号：US06081862A
公开(公告)日：2000-06-27
申请号：US140171
申请日：1998-08-26
申请人： Robert Christopher Dixon , Thoi Nguyen
发明人： Robert Christopher Dixon , Thoi Nguyen
IPC分类号： G11C5/06 , G06F1/00 , H04B3/00
CPC分类号： G11C5/063
摘要： A method and implementing system is provided which includes a switching device as part of a circuit board transmission line or trace serially connecting a plurality of device terminal sockets to a common node. When device terminals are left unconnected, corresponding segments of the connecting transmission line on the circuit board are disconnected to provide transmission line segments corresponding to the number of devices actually used. As a result, signal transition time for signals at the common node is optimized in accordance with the number of devices actually used.
摘要翻译：提供了一种方法和实现系统，其包括作为电路板传输线路的一部分的开关设备或将多个设备终端插座串行连接到公共节点的跟踪。当设备端子未连接时，电路板上的连接传输线的相应段被断开以提供对应于实际使用的设备数量的传输线段。结果，根据实际使用的设备的数量来优化公共节点处的信号的信号转换时间。

4. 发明授权

US06223309B1 Method and apparatus for ECC logic test 失效
标题翻译：用于ECC逻辑测试的方法和装置
公开(公告)号：US06223309B1
公开(公告)日：2001-04-24
申请号：US09165958
申请日：1998-10-02
申请人： Robert Christopher Dixon , Van Hoa Lee , Thoi Nguyen
发明人： Robert Christopher Dixon , Van Hoa Lee , Thoi Nguyen
IPC分类号： G06F1100
CPC分类号： G06F11/2215 , G06F11/1048
摘要： An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus. The test state applied to the check bits line varies from the check bit state that would be generated by the ECC unit of the computer system upon receiving the test state that is applied to the data bit lines.
摘要翻译： ECC验证电路，包括被配置为输出预定逻辑信号的第一偏置电路。验证电路还包括连接在计算机系统的存储器数据总线的第一偏置电路和第一数据位线之间的开关。存储器数据总线包括多个数据位线和多个校验位线，并且计算机系统包括耦合到存储器数据总线的纠错电路。验证电路被配置为在计算机系统的验证周期期间激活交换机。以这种方式，在验证周期期间将预定的逻辑信号施加到第一数据位线。验证电路被设计为将测试状态应用于数据位线并检查存储器数据总线的位线。应用于校验位线的测试状态随着计算机系统的ECC单元在接收到应用于数据位线的测试状态时将产生的校验位状态变化。

5. 发明授权

US6115773A Circuit for detecting improper bus termination on a SCSI bus 失效
标题翻译：用于检测SCSI总线上不正确的总线终端的电路
公开(公告)号：US6115773A
公开(公告)日：2000-09-05
申请号：US159958
申请日：1998-09-24
申请人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Thoi Nguyen , Khuong Huu Pham
发明人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Thoi Nguyen , Khuong Huu Pham
IPC分类号： G06F13/40 , G06F13/00 , G01R27/00 , H03K19/08
CPC分类号： G06F13/4086
摘要： A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus. An excess or shortage of termination circuits connected to the bus will result in a detected control signal voltage that is not within the specified limits.
摘要翻译：总线终端阻抗验证电路。验证电路包括由感测输入节点和感测输出节点组成的检测电路。感测电路的感测节点连接到总线的信号导体，以检测总线的终端阻抗。当感测电路输入节点被激活时，感测输出节点的电压指示总线的终端阻抗。比较器电路包括比较器输入节点和比较器输出节点。比较器输入节点连接到感测电路输出节点。比较器电路被配置为使得比较器输出节点指示比较器输入节点的电压是否在规定的电压范围内。由感测电路检测到的信号导体的电压将是连接到总线的终端电路的阻抗的函数。连接到总线的终端电路的过剩或不足将导致检测到的控制信号电压不在规定的限度内。

6. 发明授权

US6016517A Data processing system and method for optimizing connector usage 失效
标题翻译：用于优化连接器使用的数据处理系统和方法
公开(公告)号：US6016517A
公开(公告)日：2000-01-18
申请号：US827743
申请日：1997-04-10
申请人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Josefina Santiago Drerup , Thoi Nguyen
发明人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Josefina Santiago Drerup , Thoi Nguyen
IPC分类号： G06F1/22 , H03K19/173 , G06F13/00
CPC分类号： G06F1/22 , H03K19/1732
摘要： A connector on a printed circuit board of a computer system is reused to reduce a number of connectors utilized on a motherboard of a computer system. By recognizing that some signals are common between a programming application performed during a manufacturing process and a second application performed while the computer system is a normal customer operation, the connector may be used to provide data values during both the manufacturing process and normal customer operation. Stated another way, data signals used to drive programmed data during the manufacturing process may be re-used to provide serial data to an input/output device during normal customer operation.
摘要翻译：重新使用计算机系统的印刷电路板上的连接器来减少在计算机系统的主板上使用的多个连接器。通过认识到在制造过程中执行的编程应用和在计算机系统是正常客户操作期间执行的第二应用之间的一些信号是共同的，连接器可以用于在制造过程和正常客户操作期间提供数据值。换句话说，用于在制造过程中驱动编程数据的数据信号可能被重新用于在正常的客户操作期间向输入/输出设备提供串行数据。

7. 发明授权

US5953243A Memory module identification 失效
标题翻译：内存模块识别
公开(公告)号：US5953243A
公开(公告)日：1999-09-14
申请号：US164131
申请日：1998-09-30
申请人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Van Hoa Lee , Thoi Nguyen
发明人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Van Hoa Lee , Thoi Nguyen
IPC分类号： G06F1/00 , G06F11/00 , G06F13/42 , G11C5/00 , G11C5/02
CPC分类号： G11C5/06 , G06F11/006 , G06F13/4239 , G11C5/04
摘要： A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.
摘要翻译：计算机系统包括具有能够接收DRAM和SDRAM存储器模块设备的DIMM插槽的存储器子系统。存储器件检测方法检测存储器模块插槽中存在的已安装的存储器模块，并且处理所安装的存储器模块的预定引脚上的信号电平以识别所安装的存储器模块的具体类型。相关联的存储器控制器的模式根据检测到的模块的类型来设置，并且读取存储器模块的特性。

8. 发明授权

US07734444B2 Systems and arrangements to assess thermal performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US07734444B2
公开(公告)日：2010-06-08
申请号：US11937710
申请日：2007-11-09
申请人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
发明人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
IPC分类号： G01K17/00
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

9. 发明申请

US20060263912A1 Systems and arrangements to assess thermal performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US20060263912A1
公开(公告)日：2006-11-23
申请号：US11133427
申请日：2005-05-19
申请人： Ronald Arroyo , Kenneth Bird , William Ciarfella , Bret Elison , Gary Goth , Terrance Kueper , Thoi Nguyen , Roger Weekly
发明人： Ronald Arroyo , Kenneth Bird , William Ciarfella , Bret Elison , Gary Goth , Terrance Kueper , Thoi Nguyen , Roger Weekly
IPC分类号： H01L21/66 , G01N25/68 , G01N25/00 , G01K15/00
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

10. 发明授权

US5768550A Bus interface logic system 失效
标题翻译：总线接口逻辑系统
公开(公告)号：US5768550A
公开(公告)日：1998-06-16
申请号：US560758
申请日：1995-11-21
申请人： Mark Edward Dean , Thoi Nguyen
发明人： Mark Edward Dean , Thoi Nguyen
IPC分类号： G06F15/16 , G06F13/36 , G06F13/38 , G06F13/40 , G06F15/177 , G06F13/00
CPC分类号： G06F13/36 , G06F13/4027
摘要： A system and method of synchronizing data transfers between two processors having different bus transactions by providing a buffer for storing the data and a control logic for dividing a concurrent address and data bus transactions into an address bus transaction followed by a data bus transaction. During a read operation, the requesting device is forced to wait for data availability before entering the data bus transaction. During a write operation, the data bus transaction is delayed by using a storage mechanism that effectively separates the address transaction from the data transaction. The present invention also provides direct memory access fly-by operations between an input/output device and a memory device. These operations are accomplished by isolating a secondary bus from the system bus and allowing the destination device to capture the requested data as soon as it is available on the system bus.
摘要翻译：一种通过提供用于存储数据的缓冲器和用于将并发地址和数据总线事务划分为地址总线事务以及数据总线事务的控制逻辑来同步具有不同总线事务的两个处理器之间的数据传输的系统和方法。在读取操作期间，请求设备在进入数据总线事务之前被迫等待数据可用性。在写入操作期间，通过使用有效地将地址事务与数据事务分离的存储机制来延迟数据总线事务。本发明还提供了在输入/输出设备和存储设备之间的直接存储器访问飞越操作。这些操作通过将二次总线与系统总线隔离并允许目标设备在系统总线上可用时捕获所请求的数据来实现。

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