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1. 发明授权

US07734444B2 Systems and arrangements to assess thermal performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US07734444B2
公开(公告)日：2010-06-08
申请号：US11937710
申请日：2007-11-09
申请人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
发明人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
IPC分类号： G01K17/00
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

2. 发明申请

US20080112456A1 Systems and Arrangements to Assess Thermal Performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US20080112456A1
公开(公告)日：2008-05-15
申请号：US11937710
申请日：2007-11-09
申请人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
发明人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
IPC分类号： G01N25/00
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

3. 发明授权

US07338818B2 Systems and arrangements to assess thermal performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US07338818B2
公开(公告)日：2008-03-04
申请号：US11133427
申请日：2005-05-19
申请人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
发明人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
IPC分类号： H01L21/66
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

4. 发明授权

US07696565B2 FinFET body contact structure 有权
标题翻译： FinFET体接触结构
公开(公告)号：US07696565B2
公开(公告)日：2010-04-13
申请号：US11696331
申请日：2007-04-04
申请人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

5. 发明授权

US07241649B2 FinFET body contact structure 有权
标题翻译： FinFET体接触结构
公开(公告)号：US07241649B2
公开(公告)日：2007-07-10
申请号：US10977768
申请日：2004-10-29
申请人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , Karl Robert Erickson , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

6. 发明授权

US06198316B1 CMOS off-chip driver circuit 失效
标题翻译： CMOS片外驱动电路
公开(公告)号：US06198316B1
公开(公告)日：2001-03-06
申请号：US09397249
申请日：1999-09-16
申请人： David John Krolak , Terrance Wayne Kueper
发明人： David John Krolak , Terrance Wayne Kueper
IPC分类号： H03B100
CPC分类号： H03K19/00315
摘要： An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and second input nodes for receiving a first and second input signal respectively. An input composite transmission gate including a p-channel transistor in parallel with an n-channel transistor to receive the first input signal is provided in the circuit. A push-pull circuit is also included which includes the pull-up transistor disposed between a voltage supply and an output node and a first pull-down transistor disposed between ground and the output node. The pull-up transistor has a gate electrode for receiving the first input signal provided by the input composite transmission gate. The first pull-down transistor has a gate electrode for receiving the second input signal. A control transistor is included and is coupled between the gate electrode of the pull-up transistor and the output node. The control transistor has a gate electrode connected to a first point of reference potential. An auxiliary transistor is provided coupled between the first input node and a gate electrode of the p-channel transistor for establishing and maintaining a voltage at the gate electrode of the p-channel transistor during a transition of the circuit from an active mode to a high impedance mode sufficient to provide a proper transition from the active mode to the high impedance mode. A biasing transistor is also provided having a gate electrode directly connected to the output node and coupled to the voltage supply for biasing an N-well in which the pull-up transistor, the control transistor, and the auxiliary transistor are situated.
摘要翻译：公开了一种改进的片外驱动电路，其将适当地从有源模式转换到高阻抗模式。电路包括用于分别接收第一和第二输入信号的第一和第二输入节点。在电路中提供包括与n沟道晶体管并联的p沟道晶体管以接收第一输入信号的输入复合传输门。还包括推挽电路，其包括设置在电压源和输出节点之间的上拉晶体管和设置在地和输出节点之间的第一下拉晶体管。上拉晶体管具有用于接收由输入复合传输门提供的第一输入信号的栅电极。第一下拉晶体管具有用于接收第二输入信号的栅电极。包括一个控制晶体管，并且耦合在上拉晶体管的栅电极和输出节点之间。控制晶体管具有连接到第一参考电位点的栅电极。辅助晶体管被耦合在第一输入节点和p沟道晶体管的栅电极之间，用于在电路从有源模式转换到高电平期间建立和维持p沟道晶体管的栅电极处的电压阻抗模式足以提供从有源模式到高阻抗模式的适当转换。还提供一种偏置晶体管，其栅极电极直接连接到输出节点并耦合到电压源，用于偏置上拉晶体管，控制晶体管和辅助晶体管所在的N阱。

7. 发明授权

US07935629B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07935629B2
公开(公告)日：2011-05-03
申请号：US11876230
申请日：2007-10-22
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

8. 发明授权

US07626220B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07626220B2
公开(公告)日：2009-12-01
申请号：US11876379
申请日：2007-10-22
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

9. 发明授权

US07317605B2 Method and apparatus for improving performance margin in logic paths 失效
标题翻译：提高逻辑路径性能余量的方法和装置
公开(公告)号：US07317605B2
公开(公告)日：2008-01-08
申请号：US10798911
申请日：2004-03-11
申请人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H02H5/04
CPC分类号： G11C5/147 , G06F1/206 , G06F1/26 , G11C7/04 , G11C11/4074
摘要： An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present invention store product data on each particular chip. The product data includes, for examples, but not limited to, a voltage range having a low limit voltage and a high limit voltage, a limit temperature, and performance of the particular chip in storage for the particular chip. Each chip has a voltage controller, a timer, and a thermal monitor. The voltage controller communicates with a voltage regulator and dynamically causes a voltage supply coupled to the chip to be as high as possible in the voltage range, subject to the limit temperature.
摘要翻译：公开了一种用于改善半导体芯片上的逻辑路径的时序余量的装置和方法。诸如CMOS（互补金属氧化物半导体）的典型逻辑实施例具有随着电源电压增加而变短的路径延迟。本发明的实施例将产品数据存储在每个特定芯片上。产品数据包括例如但不限于具有用于特定芯片的存储器中的特定芯片的低限电压和上限电压，极限温度和性能的电压范围。每个芯片都有一个电压控制器，一个定时器和一个热量监视器。电压控制器与电压调节器通信，动态地使耦合到芯片的电压在电压范围内尽可能高，受限于极限温度。

10. 发明授权

US07227183B2 Polysilicon conductor width measurement for 3-dimensional FETs 失效
标题翻译：三维FET的多晶硅导体宽度测量
公开(公告)号：US07227183B2
公开(公告)日：2007-06-05
申请号：US10944622
申请日：2004-09-17
申请人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
发明人： Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II , Jon Robert Tetzloff
IPC分类号： H01L21/66
CPC分类号： H01L27/1203 , H01L22/34 , H01L29/785
摘要： An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
摘要翻译：公开了一种用于确定三维场效应晶体管（FinFET）的多晶硅导体宽度的装置和方法。使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。第一电阻器具有第一线宽度。第二电阻具有第二线宽。第二行宽度与第一行宽度略有不同。有利地，第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。复合测试结构不仅允许计算多晶硅导体宽度，而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。

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