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1. 发明授权

US06182230B2 Active accelerated discharge of a capacitive system 失效
标题翻译：电容系统的主动加速放电
公开(公告)号：US06182230B2
公开(公告)日：2001-01-30
申请号：US09165959
申请日：1998-10-02
申请人： Ghadir Robert Gholami , Khuong Huu Pham
发明人： Ghadir Robert Gholami , Khuong Huu Pham
IPC分类号： G06F126
CPC分类号： G06F1/30
摘要： An active circuit for rapidly discharging stored energy in a capacitive system. The circuit is comprised of a variable impedance circuit, a voltage detector, and a time delay circuit. The variable impedance circuit includes a variable impedance output path configured to be connected between a Vcc bus of the capacitive system and ground. The voltage detector circuit includes an input coupled to the Vcc bus and an output connected to an input of the variable impedance circuit. The voltage detector circuit is configured to maintain the variable impedance output path in a high impedance condition while the Vcc voltage remains above a predetermined minimum value. The time delay circuit is coupled to the input of the variable impedance circuit and configured to maintain the variable impedance output path in a low impedance condition for a duration after the voltage of the Vcc bus drops below the predetermined minimum.
摘要翻译：用于在容性系统中快速放电存储的能量的有源电路。该电路由可变阻抗电路，电压检测器和时间延迟电路组成。可变阻抗电路包括可变阻抗输出路径，其被配置为连接在电容系统的Vcc总线与地之间。电压检测器电路包括耦合到Vcc总线的输入端和连接到可变阻抗电路的输入端的输出端。电压检测器电路被配置为将可变阻抗输出路径保持在高阻抗状态，同时Vcc电压保持在预定的最小值以上。时间延迟电路耦合到可变阻抗电路的输入，并被配置为在Vcc总线的电压下降到预定最小值之前的持续时间内将可变阻抗输出路径保持在低阻抗状态。

2. 发明授权

US5802355A Multi-processor system using processors of different speeds 失效
标题翻译：多处理器系统采用不同速度的处理器
公开(公告)号：US5802355A
公开(公告)日：1998-09-01
申请号：US762907
申请日：1996-12-10
申请人： Ronald Xavier Arroyo , Khuong Huu Pham
发明人： Ronald Xavier Arroyo , Khuong Huu Pham
IPC分类号： G06F1/08 , G06F15/16 , G06F1/04
CPC分类号： G06F1/08
摘要： A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.
摘要翻译：公开了允许在多处理器系统中使用不同速度的处理器的方法和装置。该方法和装置包括可编程阵列逻辑（PAL）或现场可编程门阵列（FPGA），其检测每个处理器的最大速度并选择所有处理器共同的速度作为处理器的操作速度。该方法和装置还调整系统时钟以匹配处理器的速度。

3. 发明授权

US6115773A Circuit for detecting improper bus termination on a SCSI bus 失效
标题翻译：用于检测SCSI总线上不正确的总线终端的电路
公开(公告)号：US6115773A
公开(公告)日：2000-09-05
申请号：US159958
申请日：1998-09-24
申请人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Thoi Nguyen , Khuong Huu Pham
发明人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Thoi Nguyen , Khuong Huu Pham
IPC分类号： G06F13/40 , G06F13/00 , G01R27/00 , H03K19/08
CPC分类号： G06F13/4086
摘要： A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus. An excess or shortage of termination circuits connected to the bus will result in a detected control signal voltage that is not within the specified limits.
摘要翻译：总线终端阻抗验证电路。验证电路包括由感测输入节点和感测输出节点组成的检测电路。感测电路的感测节点连接到总线的信号导体，以检测总线的终端阻抗。当感测电路输入节点被激活时，感测输出节点的电压指示总线的终端阻抗。比较器电路包括比较器输入节点和比较器输出节点。比较器输入节点连接到感测电路输出节点。比较器电路被配置为使得比较器输出节点指示比较器输入节点的电压是否在规定的电压范围内。由感测电路检测到的信号导体的电压将是连接到总线的终端电路的阻抗的函数。连接到总线的终端电路的过剩或不足将导致检测到的控制信号电压不在规定的限度内。

4. 发明授权

US6069850A Method and apparatus for driving a battery-backed up clock while a system is powered-down 失效
标题翻译：在系统关机时驱动电池备用时钟的方法和装置
公开(公告)号：US6069850A
公开(公告)日：2000-05-30
申请号：US40430
申请日：1998-03-18
申请人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Khuong Huu Pham
发明人： Louis Bennie Capps, Jr. , Robert Christopher Dixon , Khuong Huu Pham
IPC分类号： G06F1/04 , G04G19/10 , G06F1/14 , G04G5/00
CPC分类号： G04G19/10 , G06F1/14
摘要： A method and apparatus for driving a battery-backed up clock while a computer system is powered-down. The present invention uses an auxiliary power supply, VAUX, to power a microprocessor bus oscillator. The microprocessor bus oscillator is typically a high frequency, highly accurate oscillator. The microprocessor bus oscillator continues to run while the computer system is powered down, but is connected to a wall outlet. Thus, it can be used to synthesize an accurate time base to drive a battery-backed up clock input. A microcontroller, PAL, or other such circuit can be used to convert the high frequency signal from the microprocessor bus oscillator to a frequency suitable for the battery-backed up clock. Thus, a single oscillator is used to keep time for normal operations. Only when the system is moved, or when main power fails, is a battery backed-up crystal oscillator used to keep time. This minimizes the occurrence of timing errors, due to the system being turned off and back on.
摘要翻译：一种用于在计算机系统断电时驱动电池备份的时钟的方法和装置。本发明使用辅助电源VAUX为微处理器总线振荡器供电。微处理器总线振荡器通常是高频率，高精度的振荡器。当计算机系统掉电时，微处理器总线振荡器继续运行，但连接到墙上插座。因此，它可以用于合成准确的时基来驱动电池备份的时钟输入。可以使用微控制器，PAL或其它这样的电路将来自微处理器总线振荡器的高频信号转换成适合于电池备份时钟的频率。因此，使用单个振荡器来保持正常操作的时间。只有当系统移动或主电源故障时，才能使用电池备份的晶体振荡器来保持时间。由于系统被关闭并重新启动，因此最小化定时错误的发生。

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