专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07426625B2 Data processing system and computer program product for support of system memory addresses with holes 失效
标题翻译：数据处理系统和计算机程序产品，用于支持具有孔的系统内存地址
公开(公告)号：US07426625B2
公开(公告)日：2008-09-16
申请号：US10814733
申请日：2004-03-31
申请人： Van Hoa Lee
发明人： Van Hoa Lee
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/0292 , G06F12/10
摘要： A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning is virtualized to produce a first logical address range. A second physical address range allocated for system memory for the operating system is virtualized to produce a second logical address range. The first physical address range and the second physical address range are non-contiguous. Virtualization of the first and second physical address ranges is had such that the first logical address range and the second logical address range are contiguous. A memory mapped input/output physical address range that is intermediate the first physical address range and the second physical address range is virtualized to produce a third logical address range. A lowermost logical address of the third logical address range exceeds a respective upper most logical address of the first and second logical address ranges.
摘要翻译：提供了一种用于支持具有孔的存储器地址的方法，计算机程序产品和数据处理系统。被配置为支持逻辑分区的处理器运行的由操作系统分配的系统存储器的第一物理地址范围被虚拟化以产生第一逻辑地址范围。分配给操作系统的系统存储器的第二物理地址范围被虚拟化以产生第二逻辑地址范围。第一个物理地址范围和第二个物理地址范围是不连续的。使第一和第二物理地址范围的虚拟化使得第一逻辑地址范围和第二逻辑地址范围是连续的。在第一物理地址范围和第二物理地址范围之间的存储器映射的输入/输出物理地址范围被虚拟化以产生第三逻辑地址范围。第三逻辑地址范围的最低逻辑地址超过第一和第二逻辑地址范围的相应最高逻辑地址。

2. 发明申请

US20080189509A1 Data Processing System and Computer Program Product to Allow PCI Host Bridge (PHB) to Handle Pre-Fetch Read Transactions on the PCI Bus Which Access System Memory Through Translation Control Entry (TCE) Table 失效
标题翻译：数据处理系统和计算机程序产品允许PCI主机桥（PHB）在PCI总线处理预取读取事务，哪些访问系统内存通过转换控制条目（TCE）表
公开(公告)号：US20080189509A1
公开(公告)日：2008-08-07
申请号：US12105113
申请日：2008-04-17
申请人： Van Hoa Lee
发明人： Van Hoa Lee
IPC分类号： G06F12/10
CPC分类号： G06F12/0292 , G06F12/0284
摘要： A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. The mechanism of the present invention reserves a page in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid as well as contain the corresponding address of the reserved page. In this manner, all supported DMA page addresses will have valid TCE entries which translate the DMA addresses into the reserved page memory. Thus, prefetched DMA addresses will not encounter invalid DMA address translation, and crash the system.
摘要翻译：一种方法，系统和计算机指令，用于在TCE表中为所有支持的DMA地址提供有效的转换条目，以防止由于预取而发生系统错误。本发明的机制在系统存储器中保留页面。该保留页面对操作系统不可用，并且可能不被系统中的任何软件使用。保留页面也写入所有字节设置为0xFF。系统固件然后在系统存储器中为TCE表选择一个区域。初始化TCE表，TCE表中的所有条目初始化为有效，并包含保留页面的相应地址。以这种方式，所有支持的DMA页面地址将具有将DMA地址转换为保留页存储器的有效TCE条目。因此，预取的DMA地址不会遇到无效的DMA地址转换，并且系统崩溃。

3. 发明授权

US07065761B2 Nonvolatile logical partition system data management 失效
公开(公告)号：US07065761B2
公开(公告)日：2006-06-20
申请号：US09798204
申请日：2001-03-01
申请人： Robert Kimberlin Foster , Van Hoa Lee , Timothy Albert Smith , David R. Willoughby
发明人： Robert Kimberlin Foster , Van Hoa Lee , Timothy Albert Smith , David R. Willoughby
IPC分类号： G06F9/46
CPC分类号： G06F9/5016 , G06F9/4401
摘要： A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running independently from the other logical partitions. The system also includes a console coupled to the computer system for accepting logical partition configuration data input by an operator. The configuration data entered by the operator specifies the processors, I/O, and memory allocated to each logical partition defined for the system. The system further includes a set of tables maintained in the nonvolatile memory for storing the logical partition configuration data, such that the logical partition configuration data is persistent across system power cycles.

4. 发明授权

US06981079B2 Critical datapath error handling in a multiprocessor architecture 失效
标题翻译：多处理器架构中的关键数据路径错误处理
公开(公告)号：US06981079B2
公开(公告)日：2005-12-27
申请号：US10105125
申请日：2002-03-21
申请人： George John Dawkins , Ashwini Kulkarni , Van Hoa Lee , Gordon D. McIntosh , Kanisha Patel
发明人： George John Dawkins , Ashwini Kulkarni , Van Hoa Lee , Gordon D. McIntosh , Kanisha Patel
IPC分类号： G06F9/00 , G06F9/38 , G06F9/48 , G06F11/07 , G06F13/00
CPC分类号： G06F9/3861 , G06F9/3885 , G06F9/4812 , G06F11/0712 , G06F11/0724 , G06F11/0793
摘要： A interrupt is generated for all processors in a multiprocessor system when a critical datapath experiences an error. Serialization code in the interrupt handling routine for that interrupt suspends all processors except one and places the suspended processors in a waiting queue while the one processor handles the error. After the error has been handled, the remaining processors are allow to execute the interrupt handler, which simply exits detecting no error.
摘要翻译：当关键数据路径遇到错误时，会在多处理器系统中为所有处理器生成中断。该中断的中断处理例程中的序列化代码会挂起除1个以外的所有处理器，并在一个处理器处理错误时将挂起的处理器置于等待队列中。在处理错误之后，剩下的处理器允许执行中断处理程序，它只是退出检测没有错误。

5. 发明授权

US06823375B2 Simultaneous configuration of remote input/output hubs utilizing slave processors in a multi-processor, multi-RIO hub data processing system 失效
标题翻译：在多处理器，多RIO集线器数据处理系统中同时配置利用从属处理器的远程输入/输出集线器
公开(公告)号：US06823375B2
公开(公告)日：2004-11-23
申请号：US09798163
申请日：2001-03-01
申请人： Van Hoa Lee , Kiet Anh Tran
发明人： Van Hoa Lee , Kiet Anh Tran
IPC分类号： G06F15177
CPC分类号： G06F15/177
摘要： A method, system, and product are described for configuring remote input/output (RIO) hubs within a data processing system. Each one of the RIO hubs is assigned to one of multiple slave processors which are included within the data processing system. Each one of the slave processors which has an assigned RIO hub then configures its assigned RIO hub. Each RIO hub has an associated data structure that is updated with current configuration information by the slave processor assigned to configure that RIO hub. When the slave processor has finished configuring its assigned RIO hub, the slave processor then sets a configuration flag to indicate the completion of the configuration of the RIO hub.
摘要翻译：描述了在数据处理系统内配置远程输入/输出（RIO）集线器的方法，系统和产品。每个RIO集线器被分配给包括在数据处理系统内的多个从属处理器之一。每个具有分配的RIO集线器的从属处理器然后配置其分配的RIO集线器。每个RIO集线器都有一个关联的数据结构，由配置为该RIO集线器的从属处理器的当前配置信息进行更新。当从属处理器完成配置其分配的RIO集线器后，从属处理器将设置一个配置标志，以指示RIO集线器的配置完成。

6. 发明授权

US06820207B2 Method for rebooting only a specific logical partition in a data processing system as per a request for reboot 有权
标题翻译：根据重新启动请求仅重新启动数据处理系统中特定逻辑分区的方法
公开(公告)号：US06820207B2
公开(公告)日：2004-11-16
申请号：US09798167
申请日：2001-03-01
申请人： George John Dawkins , Van Hoa Lee , Kanisha Patel , Peter Dinh Phan , David R. Willoughby
发明人： George John Dawkins , Van Hoa Lee , Kanisha Patel , Peter Dinh Phan , David R. Willoughby
IPC分类号： G06F126
CPC分类号： G06F9/442 , G06F9/45558 , G06F2009/45575
摘要： A method, apparatus, and computer implemented instructions for controlling power in a data processing system having a plurality of logical partitions. Responsive to receiving a request to turn off the power for a logical partition within the plurality of logical partitions in the data processing system, a determination is made as to whether an additional partition within the plurality of logical partitions is present in the data processing system. The power is turned off in the data processing system in response to a determination an additional partition within the plurality of logical partitions is absent in the data processing system. The logical partition is shut down in response to a determination that an additional partition within the plurality of logical partitions is present in the data processing system. The mechanism of the present invention also provides for rebooting logical partitions. A request is received to reboot a logical partition within the plurality of logical partitions. A reset signal is activated only for each processor assigned to the logical partition.
摘要翻译：一种用于在具有多个逻辑分区的数据处理系统中控制功率的方法，装置和计算机实现的指令。响应于接收关于数据处理系统中的多个逻辑分区内的逻辑分区的电源的请求的请求，确定数据处理系统中是否存在多个逻辑分区内的附加分区。响应于确定在数据处理系统中不存在多个逻辑分区内的附加分区，在数据处理系统中关闭电源。响应于确定多个逻辑分区中的附加分区存在于数据处理系统中，逻辑分区被关闭。本发明的机制还提供重新启动逻辑分区。接收到重新启动多个逻辑分区内的逻辑分区的请求。复位信号仅对分配给逻辑分区的每个处理器激活。

7. 发明授权

US06658594B1 Attention mechanism for immediately displaying/logging system checkpoints 有权
标题翻译：立即显示/记录系统检查点的注意机制
公开(公告)号：US06658594B1
公开(公告)日：2003-12-02
申请号：US09616142
申请日：2000-07-13
申请人： Tam D. Bui , Van Hoa Lee , Kiet Anh Tran
发明人： Tam D. Bui , Van Hoa Lee , Kiet Anh Tran
IPC分类号： G06F1100
CPC分类号： G06F11/0712 , G06F11/0766
摘要： A method, system, and apparatus of recording information generated by a data processing system prior to completion enablement of programmed input/output services for the data processing system is provided. In one embodiment, a service processor receives an attention interrupt from a host processor. The service processor then stops the operation of all host processors in the data processing system. The service processor then reads the information, such as a system checkpoint, from a buffer within the host processor's system memory and writes the information into a non-volatile random access memory as well as displays the information to a user via a video display. The service processor then restarts the host processors.
摘要翻译：提供了一种记录在数据处理系统完成之前由数据处理系统产生的信息的方法，系统和装置，使得能够为数据处理系统提供编程的输入/输出服务。在一个实施例中，服务处理器从主处理器接收注意中断。服务处理器然后停止数据处理系统中所有主机处理器的操作。然后，服务处理器从主处理器的系统存储器内的缓冲器中读取诸如系统检查点的信息，并将该信息写入非易失性随机存取存储器，并通过视频显示将信息显示给用户。然后服务处理器重启主机处理器。

8. 发明授权

US06178445B1 System and method for determining which processor is the master processor in a symmetric multi-processor environment 失效
标题翻译：用于在对称多处理器环境中确定哪个处理器是主处理器的系统和方法
公开(公告)号：US06178445B1
公开(公告)日：2001-01-23
申请号：US09052456
申请日：1998-03-31
申请人： George John Dawkins , Van Hoa Lee
发明人： George John Dawkins , Van Hoa Lee
IPC分类号： G06F1516
CPC分类号： G06F15/177 , G06F11/1417
摘要： A system and method for determining which processor is to be the master processor in a symmetric multi-processor (SMP) environment. The determination is made by boot-level code, i.e. the software program which executes first in a processor after it is brought on-line. Each processor in the SMP system is brought on-line independently of the other processors in the system, and each processor in the system can uniquely identify itself. As a processor comes on-line, it checks to see if a master processor has already been designated. If not, the processor checks to see if another processor, with a higher priority identifier, has identified itself as a working processor. If so, the processor commits to being a slave processor. If not, the processor indicates that it is available to be the master processor. A further check is made to ensure that only one processor has indicated that it is available to become the master processor. The likelihood that a particular processor will become the master processor may be increased or decreased by changing the processor's unique identifier. Thus, the system and method is controllable and changeable, without the need for any special or dedicated hardware. The probability that the system will always successfully select a master processor is increased, as is the probability that the system will initialize successfully even if one or more of the processors malfunctions.
摘要翻译：一种用于在对称多处理器（SMP）环境中确定哪个处理器是主处理器的系统和方法。由引导级代码确定，即在处理器被联机之后首先执行的软件程序。 SMP系统中的每个处理器独立于系统中的其他处理器而上线，系统中的每个处理器可以唯一地标识自身。当处理器上线时，它会检查是否已经指定了主处理器。如果没有，则处理器检查是否具有较高优先级标识符的另一处理器已经将其自身识别为工作处理器。如果是这样，则处理器将作为从属处理器。如果没有，则处理器指示它可用作主处理器。进一步检查以确保只有一个处理器已经指示它可用于成为主处理器。可以通过改变处理器的唯一标识符来增加或减少特定处理器将成为主处理器的可能性。因此，系统和方法是可控的和可变的，而不需要任何特殊或专用的硬件。系统总是成功选择主处理器的可能性会增加，即使一个或多个处理器发生故障，系统将成功初始化的可能性也会增加。

9. 发明授权

US5906002A Method and apparatus for saving and restoring the context of registers using different instruction sets for different sized registers 失效
标题翻译：用于为不同大小的寄存器使用不同的指令集来保存和恢复寄存器的上下文的方法和装置
公开(公告)号：US5906002A
公开(公告)日：1999-05-18
申请号：US799589
申请日：1997-02-10
申请人： Van Hoa Lee
发明人： Van Hoa Lee
IPC分类号： G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00
CPC分类号： G06F9/30112 , G06F9/461
摘要： A method of saving the context of a plurality of registers in a computer processor, requires determining whether the processor registers have a first size or a second size, and saving the contents of the registers in a buffer using a first set of instructions if the processor registers have the first size (e.g., 64 bits), and using a second set of instructions if the processor registers have the second size (e.g., 32 bits). If the processor registers having the first size, the method may further include the steps of determining whether the processor is operating in a first mode (e.g., 64-bit mode) or a second mode (e.g., 32-bit mode), and then saving the contents of the registers in the buffer using the first set of instructions if the processor is operating in the first mode, but using the second set of instructions if the processor is operating in the second mode. The method can additionally determine whether the processor registers have a third size, and use a third set of instructions if the processor registers have the third size. Similarly, if the processor can operate in a third mode, then the contents of the registers may be saved using a third set of instructions if the processor is operating in the third mode. The context-saving code uses a portion of the registers for its processing, by initially saving a first portion of the registers in the buffer, and thereafter using the first portion of the registers to temporarily store the contents of other registers. The contents of the other registers are later restored from the first portion of the registers, and then saved in the buffer.
摘要翻译：一种在计算机处理器中保存多个寄存器的上下文的方法需要确定处理器寄存器是否具有第一大小或第二大小，并且如果处理器使用第一组指令，则将寄存器的内容保存在缓冲器中寄存器具有第一大小（例如，64位），并且如果处理器寄存器具有第二大小（例如，32位），则使用第二组指令。如果处理器具有第一大小，则该方法还可以包括以下步骤：确定处理器是否处于第一模式（例如，64位模式）或第二模式（例如，32位模式）中，然后如果处理器在第一模式下运行，则使用第一组指令将缓冲器中的寄存器的内容保存在缓冲器中，而如果处理器在第二模式下运行则使用第二组指令。该方法还可以确定处理器寄存器是否具有第三大小，并且如果处理器寄存器具有第三大小，则使用第三组指令。类似地，如果处理器可以在第三模式下操作，则如果处理器在第三模式下操作，则可以使用第三组指令来保存寄存器的内容。上下文保存代码通过首先将缓冲器中的第一部分寄存器保存在其中，然后使用寄存器的第一部分临时存储其他寄存器的内容，使用寄存器的一部分进行处理。其他寄存器的内容稍后从寄存器的第一部分恢复，然后保存在缓冲区中。

10. 发明申请

US20090300644A1 Method to Detect a Deadlock Condition by Monitoring Firmware Inactivity During the System IPL Process 失效
标题翻译：通过监控系统IPL过程中的固件不活动性来检测死锁条件的方法
公开(公告)号：US20090300644A1
公开(公告)日：2009-12-03
申请号：US12129893
申请日：2008-05-30
申请人： Van Hoa Lee , David Dean Sanner , Alan Hlava
发明人： Van Hoa Lee , David Dean Sanner , Alan Hlava
IPC分类号： G06F9/46
CPC分类号： G06F9/524 , G06F11/0757 , G06F11/0778 , G06F11/1417
摘要： A method for managing deadlock in a data processing system during an IPL process includes monitoring the usage of locks in the Hardware Object Model (HOM) of the data processing system. The process further includes detecting a deadlock condition in response to an indication of the IPL process in the data processing system entering a hung state when at least one lock is in use. The process further includes handling the deadlock condition by performing one or more of the following: recording error information for the deadlock condition, and terminating the IPL process.
摘要翻译：一种用于在IPL处理期间管理数据处理系统中的死锁的方法包括监视数据处理系统的硬件对象模型（HOM）中的锁的使用。该过程还包括响应于在使用至少一个锁时数据处理系统进入挂起状态的IPL处理的指示来检测死锁状况。该过程还包括通过执行以下一个或多个来处理死锁状况：记录死锁状况的错误信息，并终止IPL处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式