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1. 发明授权

US5640518A Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length 失效
标题翻译：向总线接口添加前置传输确认信号，以消除连续读写使用期间的数据总线周转，并允许未知长度的突发传输
公开(公告)号：US5640518A
公开(公告)日：1997-06-17
申请号：US588150
申请日：1996-01-18
申请人： John Stephen Muhich , Ronald Xavier Arroyo , Charles Gordon Wright , Lawrence Joseph Merkel
发明人： John Stephen Muhich , Ronald Xavier Arroyo , Charles Gordon Wright , Lawrence Joseph Merkel
IPC分类号： G06F15/16 , G06F9/52 , G06F13/28 , G06F13/30 , G06F13/362 , G06F15/177 , G06F15/78 , G06F13/00
CPC分类号： G06F13/30 , G06F13/28 , G06F13/362
摘要： A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus interface, called pre-last transfer acknowledge. The signal is asserted by the slave one cycle before the last transfer acknowledge signal is asserted. The signal is intended to be received by the system's bus arbiter. If the current data tenure and the next data tenure are both read operations directed to the same slave (such as the memory controller) or both write operations from the same master to the same slave, then the arbiter may grant the data bus to the master of the next data tenure the cycle following the assertion of the pre-last transfer acknowledge indicator. This allows the arbiter to grant the bus a cycle earlier than it normally could (where it would have to see the final transfer acknowledge signal before it could grant the bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth is increased by up to twenty percent.
摘要翻译：在微处理器总线接口中提供了一种机制，以消除在连续读取数据总线固定中涉及相同的从属单元的情况下的转向，或者在连续的写入数据总线期限中涉及相同的主机和从机的情况。一个新的可选信号被添加到总线接口，称为前置传输确认。在最后一个传输确认信号置位之前，该信号由从器件一个周期置位。该信号旨在由系统的总线仲裁器接收。如果当前的数据保有权和下一个数据保有期都是针对同一个从属（例如存储器控制器）的读取操作或者从同一个主机到同一个从机的两个写入操作，则仲裁器可以将数据总线授予主机在下一次数据保留期间，确认前置转接确认指示符之后的周期。这允许仲裁器比通常可以更早地给予总线一个周期（在它可以授予总线之前必须看到最后的传输确认信号）。因此，总线周转周期被消除，数据总线带宽增加了百分之二十。

2. 发明授权

US07734444B2 Systems and arrangements to assess thermal performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US07734444B2
公开(公告)日：2010-06-08
申请号：US11937710
申请日：2007-11-09
申请人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
发明人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
IPC分类号： G01K17/00
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

3. 发明授权

US06338119B1 Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance 有权
标题翻译：具有页面缓冲区和I / O页面禁止定义的方法和设备，用于改进DMA和L1 / L2缓存性能
公开(公告)号：US06338119B1
公开(公告)日：2002-01-08
申请号：US09282631
申请日：1999-03-31
申请人： Gary Dean Anderson , Ronald Xavier Arroyo , Bradly George Frey , Guy Lynn Guthrie
发明人： Gary Dean Anderson , Ronald Xavier Arroyo , Bradly George Frey , Guy Lynn Guthrie
IPC分类号： G06F1300
CPC分类号： G06F12/0835 , G06F13/28
摘要： A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or “I/O” page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with distinctive cache line characteristics. For Direct Memory Access (DMA) reads, the first cache line in the I/O page may be accessed, by a Peripheral Component Interconnect (PCI) Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated, the Level 1 and Level 2 ((L1/L2) caches continue to treat all cache lines in this page as cacheable). By defining the first line as cacheable, only one cache line need be invalidated on the system bus by the L1/L2 cache in order to cause invalidation of the whole page of data in the PCI Host Bridge. All stores to the other cache lines in the I/O Page can occur directly in the L1/L2 cache without system bus operations, since these lines have been left in the ‘modified’ state in the L1/L2 cache.
摘要翻译：使用定义为具有大尺寸（例如4千字节或4Kb）但具有鲜明的高速缓存行特征的特殊输入/输出或“I / O”页来改善直接存储器访问和高速缓存性能的方法和装置。对于直接存储器访问（DMA）读取，I / O页面中的第一个高速缓存行可以由外围组件互连（PCI）主机桥访问，作为可缓存读取，并且所有其他行都是非高速缓存访问（DMA读取没有意图缓存）。对于DMA写操作，PCI主机桥可以将所有缓存行访问为可缓存的。 PCI主机桥保持数据的I / O页面大小的缓存窥探粒度，这意味着如果主机桥检测到I / O页面中的任何缓存行上的存储（无效）类型的系统总线操作，则缓存数据该页面无效，级别1和级别2（（L1 / L2）高速缓存继续将该页面中的所有高速缓存行视为可缓存）。通过将第一行定义为可缓存的，L1 / L2缓存只能在系统总线上只有一条高速缓存行无效，从而导致PCI主机桥中整个数据页的无效。所有存储到I / O页面中的其他高速缓存行的存储可以直接发生在L1 / L2高速缓存中，而不需要系统总线操作，因为这些行在L1 / L2缓存中保持“修改”状态。

4. 发明授权

US5802355A Multi-processor system using processors of different speeds 失效
标题翻译：多处理器系统采用不同速度的处理器
公开(公告)号：US5802355A
公开(公告)日：1998-09-01
申请号：US762907
申请日：1996-12-10
申请人： Ronald Xavier Arroyo , Khuong Huu Pham
发明人： Ronald Xavier Arroyo , Khuong Huu Pham
IPC分类号： G06F1/08 , G06F15/16 , G06F1/04
CPC分类号： G06F1/08
摘要： A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.
摘要翻译：公开了允许在多处理器系统中使用不同速度的处理器的方法和装置。该方法和装置包括可编程阵列逻辑（PAL）或现场可编程门阵列（FPGA），其检测每个处理器的最大速度并选择所有处理器共同的速度作为处理器的操作速度。该方法和装置还调整系统时钟以匹配处理器的速度。

5. 发明申请

US20080112456A1 Systems and Arrangements to Assess Thermal Performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US20080112456A1
公开(公告)日：2008-05-15
申请号：US11937710
申请日：2007-11-09
申请人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
发明人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
IPC分类号： G01N25/00
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

6. 发明授权

US07338818B2 Systems and arrangements to assess thermal performance 有权
标题翻译：评估热性能的系统和安排
公开(公告)号：US07338818B2
公开(公告)日：2008-03-04
申请号：US11133427
申请日：2005-05-19
申请人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
发明人： Ronald Xavier Arroyo , Kenneth A. Bird , William A. Ciarfella , Bret Peter Elison , Gary Franklin Goth , Terrance Wayne Kueper , Thoi Nguyen , Roger Donell Weekly
IPC分类号： H01L21/66
CPC分类号： G01K7/425 , H01L23/34 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/16251 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.
摘要翻译：考虑到基于被测设备（DUT）根据电气性能标准进行操作的能力来评估热解决方案的热性能的系统和布置。实施例可以包括与DUT耦合以确定操作结温度的测试器。在一些实施例中，测量的结温度可以是客户安装中DUT的预期的工作结温。在其他实施例中，测试器可以包括基于测量的结温度和测试仪与客户安装之间的已知差异来计算投影的工作结温度的逻辑。在客户安装中确定DUT的工作结温后，将工作结温与最大结温进行比较，以便DUT的正常工作。有利的是，最大结温度可以基于DUT线的项目目标而变化。

7. 发明授权

US06748493B1 Method and apparatus for managing memory operations in a data processing system using a store buffer 有权
标题翻译：一种使用存储缓冲器来管理数据处理系统中的存储器操作的方法和装置
公开(公告)号：US06748493B1
公开(公告)日：2004-06-08
申请号：US09201214
申请日：1998-11-30
申请人： Ronald Xavier Arroyo , William E. Burky , Jody Bern Joyner
发明人： Ronald Xavier Arroyo , William E. Burky , Jody Bern Joyner
IPC分类号： G06F1300
CPC分类号： G06F12/0835 , G06F13/1663 , G06F13/1673
摘要： A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.
摘要翻译：共享存储器多处理器（SMP）数据处理系统包括实现在存储器控制器中的存储缓冲器，用于在数据处理系统内临时存储最近访问的存储器数据。存储器控制器包括用于维持存储器控制器的存储缓冲器和存储器之间的一致性的控制逻辑。存储器控制器的存储缓冲器被配置成一个或多个阵列，其被充分映射以处理I / O和CPU带宽要求。存储缓冲器和控制逻辑的组合作为存储器控制器中的前端操作，因为所有存储器请求首先由控制逻辑/存储缓冲器组合处理，以减少存储器延迟并通过消除某些存储器读取和增加有效的存储器带宽写操作。

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