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1. 发明授权

US06191034B1 Forming minimal size spaces in integrated circuit conductive lines 有权
标题翻译：在集成电路导线中形成最小尺寸空间
公开(公告)号：US06191034B1
公开(公告)日：2001-02-20
申请号：US09286401
申请日：1999-04-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L2144
CPC分类号： H01L21/76892 , H01L21/32139
摘要： A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.
摘要翻译：在导电线图案中形成最小间隙或空间的方法，用于通过首先在通过常规光学平版印刷在导电线上的绝缘层中形成开口，随后在开口中形成减小开口的侧壁，从而增加集成电路的密度，并且使用所述侧壁作为掩模，优选地通过蚀刻除去所述导电线图案的大小与所述减小的开口大致相等的部分。

2. 发明授权

US6046088A Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效
标题翻译：使用场隔离自对准多晶硅栅极的方法及其结果
公开(公告)号：US6046088A
公开(公告)日：2000-04-04
申请号：US985400
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762
CPC分类号： H01L21/28123 , H01L21/76224 , H01L29/6659
摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.
摘要翻译：在诸如浅氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面多晶硅门在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。

3. 发明授权

US5930659A Forming minimal size spaces in integrated circuit conductive lines 失效
标题翻译：在集成电路导线中形成最小尺寸空间
公开(公告)号：US5930659A
公开(公告)日：1999-07-27
申请号：US986098
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/321 , H01L21/768 , H01L21/3205 , H01L21/324
CPC分类号： H01L21/76888 , H01L21/32105 , H01L21/76838
摘要： A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.
摘要翻译：通过将多晶硅中期望的间隙或空间的大小的面积转换为氧化硅，然后除去氧化硅，形成多晶硅导电线图形中的最小间隙或间隔的方法，以增加集成电路的密度。优选的方法是选择性地将氧注入到多晶硅中并进行退火以将氧注入的多晶硅转化为氧化硅。作为替代方法，首先通过常规光学光刻形成覆盖在导电线上的绝缘层中的开口，随后在开口中形成侧壁以形成减小的开口，并且使用侧壁作为掩模，以通过缩小开口来覆盖氧气注入氧气并进入暴露的多晶硅导电线。在退火之后，注入的多晶硅转变成氧化硅并去除，以在多晶硅导电线图案中形成与缩小的开口大致相等的间隙或空间。代替用氧气进行全面注入，可以使用热氧化来将暴露的多晶硅转化为氧化硅。

4. 发明授权

US6146954A Minimizing transistor size in integrated circuits 失效
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US6146954A
公开(公告)日：2000-11-14
申请号：US119934
申请日：1998-07-21
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768 , H01L29/417
CPC分类号： H01L29/66545 , H01L21/2257 , H01L21/76895 , H01L29/41775 , H01L29/41783
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在FET之前和之后制造FET和局部互连件的源极和漏极来形成多晶硅栅极和局部互连之间的最小绝缘空间形成FET的栅极。在形成栅极之前去除源极和漏极之间的绝缘层的一部分。优选地，在该方法中使用在绝缘层下方的半导体衬底上的蚀刻停止层。

5. 发明授权

US6051881A Forming local interconnects in integrated circuits 失效
标题翻译：在集成电路中形成局部互连
公开(公告)号：US6051881A
公开(公告)日：2000-04-18
申请号：US986097
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L23/522 , H01L23/535 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/20 , H01L21/7681 , H01L21/76895 , H01L27/0676
摘要： A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.
摘要翻译：一种方法和所得到的器件，通过在多晶硅栅极上形成绝缘层，并利用蚀刻阻挡层保护所选择的栅极和绝缘层，从而允许在多晶硅栅极之间形成最小的绝缘空间，从而局部互连金属化的开口可以不对准，并且所选择的门将被其蚀刻屏障保护，并且不暴露于开口。此外，局部互连导电材料可以通过栅极或不相关的电阻器，而不会使栅极/电阻器短路。

6. 发明授权

US5844836A Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell 失效
标题翻译：具有通过局部互连到栅极电容器的电容增加的存储单元和用于制造这种单元的方法
公开(公告)号：US5844836A
公开(公告)日：1998-12-01
申请号：US822518
申请日：1997-03-24
申请人： Nicholas John Kepler , Asim A. Selcuk , Richard K. Klein , Craig S. Sander , John C. Holst , Christopher A. Spence , Raymond T. Lee , Stephen C. Horne
发明人： Nicholas John Kepler , Asim A. Selcuk , Richard K. Klein , Craig S. Sander , John C. Holst , Christopher A. Spence , Raymond T. Lee , Stephen C. Horne
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.
摘要翻译：在存储节点处具有增加的单元电容的静态随机存取存储器（SRAM）单元利用电容结构。电容结构包括多晶硅导电线与钨局部互连之间的电介质材料。多晶硅板各自连接到与SRAM单元相关联的横向晶体管的漏极。可以在局部互连和多晶硅导电线之间沉积诸如二氧化硅的电介质材料。电容器结构设置在与SRAM单元相关联的第一和第二N沟道下拉晶体管之间。

7. 发明授权

US5796651A Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device 失效
标题翻译：在读取操作期间使用减少的字线电压的存储器件以及访问这种存储器件的方法
公开(公告)号：US5796651A
公开(公告)日：1998-08-18
申请号：US858589
申请日：1997-05-19
申请人： Stephen C. Horne , Richard K. Klein , Asim A. Selcuk , Nicholas John Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst
发明人： Stephen C. Horne , Richard K. Klein , Asim A. Selcuk , Nicholas John Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst
IPC分类号： G11C8/08 , G11C11/418 , G11C11/419
CPC分类号： G11C11/418 , G11C8/08
摘要： A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.
摘要翻译：存储器件在读取操作期间使用减少的字线电压。存储器件包括存储单元和用于访问单元的通过晶体管。该单元包括耦合到具有与传输晶体管基本相同的导电性的下拉晶体管的存储节点。驱动电路在读取操作期间产生降低的字线电压以激活传输晶体管。减小的字线电压具有小于用于激活下拉晶体管的偏置电压的幅度的幅度。

8. 发明授权

US07026691B1 Minimizing transistor size in integrated circuits 有权
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US07026691B1
公开(公告)日：2006-04-11
申请号：US10042732
申请日：2001-04-25
申请人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L31/113 , H01L31/119 , H01L23/48
CPC分类号： H01L29/78 , H01L21/2257 , H01L21/28123 , H01L21/76895 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在形成FET之前制造FET和局部互连的源极和漏极来形成栅极和局部互连之间的最小空间 FET的栅极。

9. 发明授权

US06287953B1 Minimizing transistor size in integrated circuits 有权
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US06287953B1
公开(公告)日：2001-09-11
申请号：US09515875
申请日：2000-02-29
申请人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21336
CPC分类号： H01L29/78 , H01L21/2257 , H01L21/28123 , H01L21/76895 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在形成FET之前制造FET和局部互连的源极和漏极来形成栅极和局部互连之间的最小空间 FET的栅极。

10. 发明授权

US5959467A High speed dynamic differential logic circuit employing capacitance matching devices 失效
标题翻译：采用电容匹配器件的高速动态差分逻辑电路
公开(公告)号：US5959467A
公开(公告)日：1999-09-28
申请号：US938250
申请日：1997-09-26
申请人： Joseph G. Nolan, III , John C. Holst , Donald A. Draper
发明人： Joseph G. Nolan, III , John C. Holst , Donald A. Draper
IPC分类号： G11C7/06 , G11C7/10 , G11C7/22 , G11C8/14 , G11C11/418 , G11C29/02 , G11C29/32 , G11C29/50 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/099 , H03K19/177
CPC分类号： G11C29/026 , G11C11/418 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C7/062 , G11C7/065 , G11C7/1006 , G11C7/22 , G11C8/14 , H03K5/13 , H03L7/08 , G11C11/401 , G11C11/41 , G11C16/04 , G11C17/14 , G11C2029/5004 , G11C2029/5006 , H03K2005/00019 , H03K2005/00071 , H03L7/0995
摘要： The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line. A corresponding sourceless transistor, having a gate and a drain, but no source, is coupled to each input signal of the logic array and is programmable to the bit-bar-line by coupling the drain of the sourceless transistor to the bit-bar-line. The source-grounded transistors and the corresponding sourceless transistors are programmed identically providing substantially the same capacitance load on the bit-line and the bit-bar-line.
摘要翻译：本发明公开了一种差分逻辑电路和感测方法，其提供比现有技术更高的速度和更高密度的差分感测。将一个或多个输入信号提供给逻辑阵列，并且从逻辑阵列产生两个输出信号，其中逻辑阵列的一个输出信号是位线，逻辑阵列的一个输出信号是位线，如参考信号，其中两个信号作为输入信号提供给具有二进制输出信号的差分读出放大器。位线和位线线被预充电到相同的电压电平，并且具有小于填充驱动强度的受控输入源极接地晶体管耦合到位线。源极接地晶体管耦合到逻辑阵列的每个输入信号，并且通过将源极接地晶体管的漏极耦合到位线而可编程到位线。具有栅极和漏极但没有源极的相应的无源晶体管被耦合到逻辑阵列的每个输入信号，并且可通过将无源晶体管的漏极耦合到位 - 线。源极接地晶体管和相应的无源晶体管被编程相同地在位线和位线上提供基本相同的电容负载。

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