专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5959467A High speed dynamic differential logic circuit employing capacitance matching devices 失效
标题翻译：采用电容匹配器件的高速动态差分逻辑电路
公开(公告)号：US5959467A
公开(公告)日：1999-09-28
申请号：US938250
申请日：1997-09-26
申请人： Joseph G. Nolan, III , John C. Holst , Donald A. Draper
发明人： Joseph G. Nolan, III , John C. Holst , Donald A. Draper
IPC分类号： G11C7/06 , G11C7/10 , G11C7/22 , G11C8/14 , G11C11/418 , G11C29/02 , G11C29/32 , G11C29/50 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/099 , H03K19/177
CPC分类号： G11C29/026 , G11C11/418 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C7/062 , G11C7/065 , G11C7/1006 , G11C7/22 , G11C8/14 , H03K5/13 , H03L7/08 , G11C11/401 , G11C11/41 , G11C16/04 , G11C17/14 , G11C2029/5004 , G11C2029/5006 , H03K2005/00019 , H03K2005/00071 , H03L7/0995
摘要： The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line. A corresponding sourceless transistor, having a gate and a drain, but no source, is coupled to each input signal of the logic array and is programmable to the bit-bar-line by coupling the drain of the sourceless transistor to the bit-bar-line. The source-grounded transistors and the corresponding sourceless transistors are programmed identically providing substantially the same capacitance load on the bit-line and the bit-bar-line.
摘要翻译：本发明公开了一种差分逻辑电路和感测方法，其提供比现有技术更高的速度和更高密度的差分感测。将一个或多个输入信号提供给逻辑阵列，并且从逻辑阵列产生两个输出信号，其中逻辑阵列的一个输出信号是位线，逻辑阵列的一个输出信号是位线，如参考信号，其中两个信号作为输入信号提供给具有二进制输出信号的差分读出放大器。位线和位线线被预充电到相同的电压电平，并且具有小于填充驱动强度的受控输入源极接地晶体管耦合到位线。源极接地晶体管耦合到逻辑阵列的每个输入信号，并且通过将源极接地晶体管的漏极耦合到位线而可编程到位线。具有栅极和漏极但没有源极的相应的无源晶体管被耦合到逻辑阵列的每个输入信号，并且可通过将无源晶体管的漏极耦合到位 - 线。源极接地晶体管和相应的无源晶体管被编程相同地在位线和位线上提供基本相同的电容负载。

2. 发明授权

US4733168A Test enabling circuit for enabling overhead test circuitry in programmable devices 失效
标题翻译：测试使能电路，用于在可编程器件中启用开销测试电路
公开(公告)号：US4733168A
公开(公告)日：1988-03-22
申请号：US842272
申请日：1986-03-21
申请人： Timothy L. Blankenship , Joseph G. Nolan, III
发明人： Timothy L. Blankenship , Joseph G. Nolan, III
IPC分类号： G01R31/317 , G01R15/12
CPC分类号： G01R31/31701
摘要： A test enabling circuit for actuating specific testing circuitry contained within a programmable device, whereby the test enabling circuit and a portion of the normal operational circuits of the device share a common input pin. Because of the dual functionality of the common input pin, the test enabling circuit is designed to respond to a specified test signal, which is either of an opposing polarity, or of a higher magnitude of the same polarity with respect to the normal operational signal. The enabling circuit includes several IGFET devices arranged such that the noise margin of the enabling circuit may be adapted for accommodating varying environments of noise. ESD circuitry is included to protect the testing and test enabling circuits against electrostatic discharge.
摘要翻译：一种用于启动包含在可编程设备内的特定测试电路的测试启用电路，由此测试使能电路和设备的正常操作电路的一部分共享公共输入引脚。由于公共输入引脚的双重功能，测试使能电路被设计为响应相对于正常操作信号具有相反极性或相同极性的较大幅度的指定测试信号。使能电路包括若干个IGFET器件，其布置成使得使能电路的噪声容限可适于适应不同的噪声环境。包括ESD电路以保护测试和测试使能电路免受静电放电。

3. 发明授权

US5764096A General purpose, non-volatile reprogrammable switch 失效
标题翻译：通用，非易失性可编程开关
公开(公告)号：US5764096A
公开(公告)日：1998-06-09
申请号：US754116
申请日：1996-11-21
申请人： Robert J. Lipp , Richard D. Freeman , Robert U. Broze , John M. Caywood , Joseph G. Nolan, III
发明人： Robert J. Lipp , Richard D. Freeman , Robert U. Broze , John M. Caywood , Joseph G. Nolan, III
IPC分类号： G11C16/04 , H03K19/173 , G11C11/34
CPC分类号： H03K19/1736 , G11C16/0441
摘要： A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.
摘要翻译：一个可编程互连，将独立的开关晶体管与独立的NVM编程和擦除元件紧密集成。编程元件是EPROM晶体管，擦除元件是Fowler-Nordheim隧穿器件。一个单一的浮动栅极由开关晶体管和NVM编程和对浮动栅极充电和放电的元件共享。共享浮栅结构是集成可编程互连的存储器结构，并控制开关晶体管的阻抗。

4. 发明授权

US5671234A Programmable input/output buffer circuit with test capability 失效
标题翻译：具有测试能力的可编程输入/输出缓冲电路
公开(公告)号：US5671234A
公开(公告)日：1997-09-23
申请号：US78692
申请日：1993-06-17
申请人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
发明人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.
摘要翻译：具有可编程元件的系统逻辑的集成电路，耦合到可编程元件的解码逻辑，用于寻址可编程元件;以及多个输入/输出缓冲电路，用于通过输入/输出端子在集成电路的系统逻辑与外部之间传递信号被披露。每个输入/输出缓冲电路包括具有连接到输入/输出端子的输出端的输出驱动级; 多个单元，每个单元具有多路复用器，连接到第一多路复用器的输出端的触发器，用于存储来自第一多路复用器的信号;连接到触发器的输出端的锁存器，用于存储信号以及连接到锁存器的输出端的第二多路复用器。这些单元彼此连接，其它输入/输出缓冲电路的单元从一个单元的触发器的输出端子连接到另一个单元的第一多路复用器的第一输入端，用于通过单元串行扫描信号，以测试系统逻辑。控制线连接到单元的锁存器的输出端子和耦合到可编程元件的解码逻辑，使得可编程元件可以通过串行扫描通过单元的控制信号进行编程。

5. 发明授权

US4734886A Auxiliary word line driver for effectively controlling programmability of fusible links 失效
标题翻译：辅助字线驱动器，用于有效控制可熔链路的可编程性
公开(公告)号：US4734886A
公开(公告)日：1988-03-29
申请号：US790115
申请日：1985-10-22
申请人： Timothy L. Blankenship , Joseph G. Nolan, III
发明人： Timothy L. Blankenship , Joseph G. Nolan, III
IPC分类号： G11C5/06 , G11C8/14 , G11C17/18 , G11C17/00 , G11C17/06
CPC分类号： G11C17/18 , G11C5/063 , G11C8/14
摘要： The problem of the distributed voltage drop along a resistive word line through which fusible elements of a circuit array are selectively programmed to a state of high resistance (effective open circuit) is circumvented by incorporated an auxiliary word line driver as part of the array. The auxiliary word line driver is coupled to the word line at a location apart from the main word line driver, so as to reduce the effective resistance and consequential voltage drop along the word line. As a result, for each memory cell along a respective word line there is sufficient "rupturing current" capability, whereby each fusible element of the memory array may be successfully programmed regardless of its physical location within the array.
摘要翻译：沿着电阻字线的分布电压降的问题通过将辅助字线驱动器作为阵列的一部分而被绕过，通过该电阻字线将电路阵列的可熔元件选择性地编程到高电阻状态（有效开路）。辅助字线驱动器在远离主字线驱动器的位置处耦合到字线，以便沿字线减小有效电阻和相应的电压降。结果，对于沿着相应字线的每个存储器单元，存在足够的“破裂电流”能力，由此存储器阵列的每个可熔元件可以被成功地编程，而不管阵列内的物理位置如何。

6. 发明授权

US4698589A Test circuitry for testing fuse link programmable memory devices 失效
标题翻译：用于测试熔丝链路可编程存储器件的测试电路
公开(公告)号：US4698589A
公开(公告)日：1987-10-06
申请号：US842267
申请日：1986-03-21
申请人： Timothy L. Blankenship , Joseph G. Nolan, III
发明人： Timothy L. Blankenship , Joseph G. Nolan, III
IPC分类号： G01R31/02 , G01R31/316
CPC分类号： G01R31/026 , G01R31/02
摘要： A testing circuit for testing fuse elements in programmable memory devices. The circuit provides for testing whether the fuses have the proper resistance, both after manufacturing and after programming of the memory device. The testing circuit includes a current varying means which may include either a variable resistance or a variable current sink. The variable resistance is connected to a fuse element to form a voltage divider with the same. A sensing amplifier is connected at a node therebetween for sensing the current through the fuse element and, thus, the resistance of the same. The variable current sink provides variable current levels, thereby achieving the same above results.
摘要翻译：用于测试可编程存储器件中的熔丝元件的测试电路。该电路用于在存储器件的制造和编程之后，测试保险丝是否具有适当的电阻。测试电路包括可以包括可变电阻或可变电流吸收器的电流变化装置。可变电阻连接到熔丝元件以形成与之相同的分压器。感测放大器连接在它们之间的节点处，用于感测通过熔丝元件的电流，并因此感测其电阻。可变电流吸收器提供可变电流电平，从而实现与上述相同的结果。

7. 发明授权

US06525949B1 Charge pump circuit 有权
公开(公告)号：US06525949B1
公开(公告)日：2003-02-25
申请号：US09748815
申请日：2000-12-22
申请人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
发明人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
IPC分类号： H02M318
CPC分类号： H02M3/073
摘要： A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.

8. 发明授权

US5221865A Programmable input/output buffer circuit with test capability 失效
标题翻译：具有测试能力的可编程输入/输出缓冲电路
公开(公告)号：US5221865A
公开(公告)日：1993-06-22
申请号：US718677
申请日：1991-06-21
申请人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
发明人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the first storing means for storing a signal from the first storing means, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.
摘要翻译：具有可编程元件的系统逻辑的集成电路，耦合到可编程元件的解码逻辑，用于寻址可编程元件;以及多个输入/输出缓冲电路，用于通过输入/输出端子在集成电路的系统逻辑与外部之间传递信号被披露。每个输入/输出缓冲电路包括具有连接到输入/输出端子的输出端的输出驱动级; 以及多个单元，每个单元具有多路复用器，连接到第一多路复用器的输出端的触发器，用于存储来自第一多路复用器的信号;锁存器，连接到第一存储装置的输出端，用于存储信号以及连接到所述锁存器的输出端的第二多路复用器。这些单元彼此连接，其它输入/输出缓冲电路的单元从一个单元的触发器的输出端子连接到另一个单元的第一多路复用器的第一输入端，用于通过单元串行扫描信号，以测试系统逻辑。控制线连接到单元的锁存器的输出端子和耦合到可编程元件的解码逻辑，使得可编程元件可以通过串行扫描通过单元的控制信号进行编程。

9. 发明授权

US06483728B1 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US06483728B1
公开(公告)日：2002-11-19
申请号：US10002856
申请日：2001-11-15
申请人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
发明人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
IPC分类号： H02M318
CPC分类号： H02M3/073
摘要： A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.
摘要翻译：在优选实施例中，电荷泵电路包括多个串联连接的泵级，每个泵级由用于该级的一个或多个相关联的时钟信号驱动。与相应的泵级相关联的时钟信号的幅度与与至少一个其它泵级相关的时钟信号的振幅幅度不同。结果，每个连续的泵级实现的附加电压对于每个连续的泵级可以逐渐变大。示例性的电荷泵电路提供了每个连续的泵级增加振幅的时钟信号，并且为每个连续的泵级提供输出电压，该输出电压的幅度是该级的输入电压的幅度的乘法因子。因此，由示例性电荷泵电路实现的输出电压是电荷泵电路内的泵级数的指数函数。

10. 发明授权

US5652527A Input-output circuit for increasing immunity to voltage spikes 失效
标题翻译：输入输出电路，用于增加对电压尖峰的抗扰度
公开(公告)号：US5652527A
公开(公告)日：1997-07-29
申请号：US466556
申请日：1995-06-06
申请人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
发明人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173 , H03K19/01 , H03K19/0175
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.
摘要翻译：提供了用于增加对电压源的电压尖峰的抗扰度的输入/输出电路。电路包括第一对晶体管，每个晶体管的漏极连接到输出端，并且其源极连接到电压源。机构连接到电分离的电压源，以响应于输入信号交替地接通第一对晶体管中的一个。晶体管被用于提供反馈以限制地面反弹期间出现的接地电压供应的上升。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式