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1. 发明授权

US06600333B1 Method and test structure for characterizing sidewall damage in a semiconductor device 失效
标题翻译：用于表征半导体器件中侧壁损伤的方法和测试结构
公开(公告)号：US06600333B1
公开(公告)日：2003-07-29
申请号：US09501958
申请日：2000-02-10
申请人： Jeremy I. Martin , Nicholas J. Kepler , Larry L. Zhao
发明人： Jeremy I. Martin , Nicholas J. Kepler , Larry L. Zhao
IPC分类号： G01R2726
CPC分类号： H01L22/34 , G01R31/2884
摘要： A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared. Damage to the insulative layer is characterized based on the comparison.
摘要翻译：测试电路包括晶片，形成在晶片上的绝缘层，以及形成在绝缘层中的多个测试结构。每个测试结构包括具有第一多个指状物的第一梳子和具有第二多个指状物的第二梳子。手指的第一和第二多个交织以限定第一和第二多个手指之间的手指间隔。测试结构中第一个测试结构中的手指间距不同于第二个测试结构中的手指间距。用于表征半导体器件中的损伤的方法包括提供具有绝缘层的晶片和形成在绝缘层中的多个测试结构。测试结构具有不同的几何形状。确定多个测试结构的第一和第二测试结构的电特性。比较第一和第二测试结构的电气特性。基于比较，对绝缘层的损伤进行了表征。

2. 发明授权

US6146954A Minimizing transistor size in integrated circuits 失效
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US6146954A
公开(公告)日：2000-11-14
申请号：US119934
申请日：1998-07-21
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768 , H01L29/417
CPC分类号： H01L29/66545 , H01L21/2257 , H01L21/76895 , H01L29/41775 , H01L29/41783
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在FET之前和之后制造FET和局部互连件的源极和漏极来形成多晶硅栅极和局部互连之间的最小绝缘空间形成FET的栅极。在形成栅极之前去除源极和漏极之间的绝缘层的一部分。优选地，在该方法中使用在绝缘层下方的半导体衬底上的蚀刻停止层。

3. 发明授权

US6051881A Forming local interconnects in integrated circuits 失效
标题翻译：在集成电路中形成局部互连
公开(公告)号：US6051881A
公开(公告)日：2000-04-18
申请号：US986097
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L23/522 , H01L23/535 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/20 , H01L21/7681 , H01L21/76895 , H01L27/0676
摘要： A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.
摘要翻译：一种方法和所得到的器件，通过在多晶硅栅极上形成绝缘层，并利用蚀刻阻挡层保护所选择的栅极和绝缘层，从而允许在多晶硅栅极之间形成最小的绝缘空间，从而局部互连金属化的开口可以不对准，并且所选择的门将被其蚀刻屏障保护，并且不暴露于开口。此外，局部互连导电材料可以通过栅极或不相关的电阻器，而不会使栅极/电阻器短路。

4. 发明授权

US06406993B1 Method of defining small openings in dielectric layers 有权
标题翻译：定义介电层中小开口的方法
公开(公告)号：US06406993B1
公开(公告)日：2002-06-18
申请号：US09523439
申请日：2000-03-10
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76831
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括形成电介质材料层，在介电材料层之上形成硬掩模层，并在硬掩模层中形成开口。所述方法还包括在所述硬掩模层中的所述开口中形成侧壁间隔物，所述开口限定缩小的开口，在所述还原开口下方的介电材料层中形成开口，以及在所述电介质层的所述开口中形成导电互连。

5. 发明授权

US06287953B1 Minimizing transistor size in integrated circuits 有权
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US06287953B1
公开(公告)日：2001-09-11
申请号：US09515875
申请日：2000-02-29
申请人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21336
CPC分类号： H01L29/78 , H01L21/2257 , H01L21/28123 , H01L21/76895 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在形成FET之前制造FET和局部互连的源极和漏极来形成栅极和局部互连之间的最小空间 FET的栅极。

6. 发明授权

US5930659A Forming minimal size spaces in integrated circuit conductive lines 失效
标题翻译：在集成电路导线中形成最小尺寸空间
公开(公告)号：US5930659A
公开(公告)日：1999-07-27
申请号：US986098
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/321 , H01L21/768 , H01L21/3205 , H01L21/324
CPC分类号： H01L21/76888 , H01L21/32105 , H01L21/76838
摘要： A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.
摘要翻译：通过将多晶硅中期望的间隙或空间的大小的面积转换为氧化硅，然后除去氧化硅，形成多晶硅导电线图形中的最小间隙或间隔的方法，以增加集成电路的密度。优选的方法是选择性地将氧注入到多晶硅中并进行退火以将氧注入的多晶硅转化为氧化硅。作为替代方法，首先通过常规光学光刻形成覆盖在导电线上的绝缘层中的开口，随后在开口中形成侧壁以形成减小的开口，并且使用侧壁作为掩模，以通过缩小开口来覆盖氧气注入氧气并进入暴露的多晶硅导电线。在退火之后，注入的多晶硅转变成氧化硅并去除，以在多晶硅导电线图案中形成与缩小的开口大致相等的间隙或空间。代替用氧气进行全面注入，可以使用热氧化来将暴露的多晶硅转化为氧化硅。

7. 发明授权

US06313538B1 Semiconductor device with partial passivation layer 有权
标题翻译：具有部分钝化层的半导体器件
公开(公告)号：US06313538B1
公开(公告)日：2001-11-06
申请号：US09489479
申请日：2000-01-21
申请人： Christian Zistl , Paul R. Besser , Eric M. Apelgren , Nicholas J. Kepler , Srikanteswara Dakshina-Murthy
发明人： Christian Zistl , Paul R. Besser , Eric M. Apelgren , Nicholas J. Kepler , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76834 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.
摘要翻译：半导体器件包括第一电介质层，形成在第一电介质层中的多个导电互连，形成在导电互连之上的图案化钝化层，以及形成在钝化层和第一介电层上方并与钝化层接触的第二介电层。一种用于形成半导体器件的方法包括提供基底层，在基底层上形成第一介电层，在第一介电层中形成多个导电互连，在导电互连之上形成图案化的钝化层，以及形成第二电介质并且与钝化层和第一介电层接触。

8. 发明授权

US06191034B1 Forming minimal size spaces in integrated circuit conductive lines 有权
标题翻译：在集成电路导线中形成最小尺寸空间
公开(公告)号：US06191034B1
公开(公告)日：2001-02-20
申请号：US09286401
申请日：1999-04-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L2144
CPC分类号： H01L21/76892 , H01L21/32139
摘要： A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.
摘要翻译：在导电线图案中形成最小间隙或空间的方法，用于通过首先在通过常规光学平版印刷在导电线上的绝缘层中形成开口，随后在开口中形成减小开口的侧壁，从而增加集成电路的密度，并且使用所述侧壁作为掩模，优选地通过蚀刻除去所述导电线图案的大小与所述减小的开口大致相等的部分。

9. 发明授权

US06268255B1 Method of forming a semiconductor device with metal silicide regions 有权
标题翻译：用金属硅化物区形成半导体器件的方法
公开(公告)号：US06268255B1
公开(公告)日：2001-07-31
申请号：US09479402
申请日：2000-01-06
申请人： Paul R. Besser , Christian Zistl , Nicholas J. Kepler
发明人： Paul R. Besser , Christian Zistl , Nicholas J. Kepler
IPC分类号： H01L21336
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/6659
摘要： The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon, forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.
摘要翻译：本发明涉及制造半导体器件的方法。在一个说明性实施例中，该方法包括形成由多晶硅组成的第一层，在多晶硅层上形成由难熔金属组成的第二层，并将第二层的至少一部分转化为第一金属硅化物。该方法还包括在难熔金属层或第一金属硅化物层之上形成抗反射涂层，以及对第一金属硅化物层和多晶硅层进行构图以限定由第一金属硅化物区和多晶硅层，在衬底中形成多个源极/漏极区域，在至少栅极堆叠和源极/漏极区域上形成由难熔金属组成的第三层，并将第三层的至少一部分转化为第二金属硅化物区域。

10. 发明授权

US07026691B1 Minimizing transistor size in integrated circuits 有权
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US07026691B1
公开(公告)日：2006-04-11
申请号：US10042732
申请日：2001-04-25
申请人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L31/113 , H01L31/119 , H01L23/48
CPC分类号： H01L29/78 , H01L21/2257 , H01L21/28123 , H01L21/76895 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在形成FET之前制造FET和局部互连的源极和漏极来形成栅极和局部互连之间的最小空间 FET的栅极。

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